SAA7154E/V2/G,518 NXP Semiconductors, SAA7154E/V2/G,518 Datasheet - Page 38

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SAA7154E/V2/G,518

Manufacturer Part Number
SAA7154E/V2/G,518
Description
Manufacturer
NXP Semiconductors
Datasheet

Specifications of SAA7154E/V2/G,518

Adc/dac Resolution
10b
Screening Level
Commercial
Package Type
LBGA
Pin Count
156
Lead Free Status / RoHS Status
Compliant
NXP Semiconductors
SAA7154E_SAA7154H_2
Product data sheet
Fig 14. Vertical timing diagram for 50 Hz/625 line systems
(1) The signal HREF at the negative edge of signal V123 indicates whether this field is odd or even. If HREF is logic 1, the field
single field counting
single field counting
is odd (field 1) and if HREF is logic 0, the field is even.
The control signals are available on the pins listed in
be inverted by bits RTP0 or RTP1.
ITU counting
ITU counting
F_ITU656
F_ITU656
V123
VGATE
V123
VGATE
CVBS
HREF
CVBS
HREF
FID
FID
(1)
(1)
622
309
309
309
VSTO [ 8:0 ] = 134h
VSTO [ 8:0 ] = 134h
623
310
310
310
624
311
311
311
625
312
312
312
Rev. 02 — 6 December 2007
313
313
1
1
Table
314
2
2
1
(a) 1st field
(b) 2nd field
12. The polarity of the signals HREF, HS, CREF2 and CREF can
315
3
3
2
SAA7154E; SAA7154H
Multistandard video decoder with comb filter
316
4
4
3
317
5
5
4
318
6
6
5
319
7
7
6
. . .
. . .
. . .
. . .
VSTA [ 8:0 ] = 15h
VSTA [ 8:0 ] = 15h
335
22
22
22
© NXP B.V. 2007. All rights reserved.
mhb540
336
23
23
23
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