SAA7154E/V2/G,518 NXP Semiconductors, SAA7154E/V2/G,518 Datasheet - Page 39
SAA7154E/V2/G,518
Manufacturer Part Number
SAA7154E/V2/G,518
Description
Manufacturer
NXP Semiconductors
Datasheet
1.SAA7154EV2G518.pdf
(90 pages)
Specifications of SAA7154E/V2/G,518
Adc/dac Resolution
10b
Screening Level
Commercial
Package Type
LBGA
Pin Count
156
Lead Free Status / RoHS Status
Compliant
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NXP Semiconductors
SAA7154E_SAA7154H_2
Product data sheet
Fig 15. Vertical timing diagram for 60 Hz/525 line systems
(1) The signal HREF at the negative edge of signal V123 indicates whether this field is odd or even. If HREF is logic 1, the field
single field counting
single field counting
is odd (field 1) and if HREF is logic 0, the field is even.
The control signals are available on the pins listed in
be inverted by bits RTP0 or RTP1.
ITU counting
ITU counting
F_ITU656
F_ITU656
V123
VGATE
V123
VGATE
CVBS
HREF
CVBS
HREF
FID
FID
(1)
(1)
525
262
262
262
VSTO [ 8:0 ] = 101h
VSTO [ 8:0 ] = 101h
263
263
1
1
264
2
2
1
265
3
3
2
Rev. 02 — 6 December 2007
266
4
4
3
Table
267
5
5
4
(a) 1st field
(b) 2nd field
12. The polarity of the signals HREF, HS, CREF2 and CREF can
268
6
6
5
SAA7154E; SAA7154H
Multistandard video decoder with comb filter
269
7
7
6
270
8
8
7
271
9
9
8
272
10
10
9
. . .
. . .
. . .
. . .
VSTA [ 8:0 ] = 011h
VSTA [ 8:0 ] = 011h
284
21
21
21
© NXP B.V. 2007. All rights reserved.
mhb541
285
22
22
22
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