M368L6423FTNCB3 Samsung Semiconductor, M368L6423FTNCB3 Datasheet - Page 15

• Manufacturer Part Number: M368L6423FTNCB3
• Manufacturer: Samsung Semiconductor

Specifications of M368L6423FTNCB3

• Main Category: DRAM Module
• Sub-category: DDR SDRAM
• Module Type: 184UDIMM
• Device Core Size: 64b
• Organization: 64Mx64
• Total Density: 512MByte
• Chip Density: 256Mb
• Access Time (max): 700ps
• Maximum Clock Rate: 333MHz
• Operating Supply Voltage (typ): 2.5V
• Operating Current: 1.72A
• Number Of Elements: 16
• Operating Supply Voltage (max): 2.7V
• Operating Supply Voltage (min): 2.3V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Pin Count: 184
• Mounting: Socket
• Lead Free Status / RoHS Status: Not Compliant

10.0 AC Operating Conditions
Note :
1. VID is the magnitude of the difference between the input level on CK and the input on CK.
2. The value of V
3. These parameters should be tested at the pim on actual components and may be checked at either the pin or the pad in
11.0 Input/Output Capacitance
Input capacitance(A0 ~ A12, BA0 ~ BA1,RAS,CAS,WE )
Input capacitance(CKE0)
Input capacitance( CS0)
Input capacitance( CLK0, CLK1,CLK2)
Input capacitance(DM0~DM7, DM8(for ECC))
Data & DQS input/output capacitance(DQ0~DQ63)
Data input/output capacitance (CB0~CB7)
Input capacitance(A0 ~ A12, BA0 ~ BA1,RAS,CAS,WE )
Input capacitance(CKE0,CKE1)
Input capacitance( CS0, CS1)
Input capacitance( CLK0, CLK1,CLK2)
Input capacitance(DM0~DM7, DM8(for ECC))
Data & DQS input/output capacitance(DQ0~DQ63)
Data input/output capacitance (CB0~CB7)
128MB, 256MB, 512MB Unbuffered DIMM
simulation. the AC and DC input specificatims are refation to a Vref envelope that has been bandwidth limited 20MHz.
Input High (Logic 1) Voltage, DQ, DQS and DM signals
Input Low (Logic 0) Voltage, DQ, DQS and DM signals.
Input Crossing Point Voltage, CK and CK inputs
Input Differential Voltage, CK and CK inputs
IX
is expected to equal 0.5*V
Parameter/Condition
Parameter
Parameter
Output
DDQ
of the transmitting device and must track variations in the DC level of the same.
Output Load Circuit (SSTL_2)
Z0=50Ω
Symbol
Symbol
C
Cout1
Cout2
Cout1
Cout2
CIN1
CIN2
CIN3
CIN4
CIN5
CIN1
CIN2
CIN3
CIN4
CIN5
LOAD
=30pF
V
tt
VIH(AC)
VID(AC)
VIX(AC)
M368L1624FT(U) M368L3223FT(U) M381L3223FT(U)
Symbol
VIL(AC)
=0.5*V
Min
41
34
34
25
6
6
-
Min
M368L6423FT(U)
65
42
42
28
10
10
-
R
DDQ
T
=50Ω
0.5*VDDQ-0.2
Max
VREF + 0.31
V
=0.5*V
45
38
38
30
7
7
-
REF
Min
0.7
DDQ
Max
81
50
50
34
12
12
-
(VDD=2.5V, VDDQ=2.5V, TA= 25°C, f=1MHz)
Min
49
42
42
25
6
6
-
0.5*VDDQ+0.2
VREF - 0.31
VDDQ+0.6
Max
57
50
50
30
7
7
-
Max
Min
M381L6423FT(U)
44
69
44
28
10
10
10
Rev. 1.3 July 2005
Min
51
44
44
25
DDR SDRAM
6
6
6
Unit
Max
87
53
53
34
12
12
12
V
V
V
V
Max
60
53
53
30
7
7
7
Note
Unit
Unit
3
3
1
2
pF
pF
pF
pF
pF
pF
pF
pF
pF
pF
pF
pF
pF
pF