M368L6423FTNCB3 Samsung Semiconductor, M368L6423FTNCB3 Datasheet - Page 16

• Manufacturer Part Number: M368L6423FTNCB3
• Manufacturer: Samsung Semiconductor

Specifications of M368L6423FTNCB3

• Main Category: DRAM Module
• Sub-category: DDR SDRAM
• Module Type: 184UDIMM
• Device Core Size: 64b
• Organization: 64Mx64
• Total Density: 512MByte
• Chip Density: 256Mb
• Access Time (max): 700ps
• Maximum Clock Rate: 333MHz
• Operating Supply Voltage (typ): 2.5V
• Operating Current: 1.72A
• Number Of Elements: 16
• Operating Supply Voltage (max): 2.7V
• Operating Supply Voltage (min): 2.3V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Pin Count: 184
• Mounting: Socket
• Lead Free Status / RoHS Status: Not Compliant

12.0 AC Timming Parameters & Specifications
128MB, 256MB, 512MB Unbuffered DIMM
Row cycle time
Refresh row cycle time
Row active time
RAS to CAS delay
Row precharge time
Row active to Row active delay
Write recovery time
Last data in to Read command
Clock cycle time
Clock high level width
Clock low level width
DQS-out access time from CK/CK
Output data access time from CK/CK
Data strobe edge to ouput data edge
Read Preamble
Read Postamble
CK to valid DQS-in
DQS-in setup time
DQS-in hold time
DQS falling edge to CK rising-setup time
DQS falling edge from CK rising-hold time
DQS-in high level width
DQS-in low level width
Address and Control Input setup time(fast)
Address and Control Input hold time(fast)
Address and Control Input setup time(slow)
Address and Control Input hold time(slow)
Data-out high impedence time from CK/CK
Data-out low impedence time from CK/CK
Mode register set cycle time
DQ & DM setup time to DQS
DQ & DM hold time to DQS
Control & Address input pulse width
DQ & DM input pulse width
Exit self refresh to non-Read command
Exit self refresh to read command
Refresh interval time
Output DQS valid window
Clock half period
Data hold skew factor
DQS write postamble time
Active to Read with Auto precharge
command
Autoprecharge write recovery +
Precharge time
Parameter
CL=2.0
CL=2.5
CL=3.0
Symbol
tWPRES
tDQSCK
tWPRE
tDQSQ
tDQSS
tDQSH
tWPST
tRPRE
tRPST
tDQSL
tXSNR
tXSRD
tDIPW
tWTR
tMRD
tREFI
tRFC
tRAS
tRCD
tRRD
tDSS
tDSH
tQHS
tRAP
tIPW
tDAL
tWR
tRC
tCH
tDH
tQH
tRP
tCK
tCL
tAC
tHZ
tDS
tHP
tLZ
tIH
tIH
tIS
tIS
or tCHmin
(tWR/tCK)
(tRP/tCK)
(DDR400@CL=3.0)
tCLmin
-tQHS
-0.55
-0.65
-0.65
-0.65
Min
0.45
0.45
0.72
0.25
0.35
0.35
1.75
200
tHP
0.9
0.4
0.2
0.2
0.6
0.6
0.7
0.7
0.4
0.4
2.2
0.4
55
70
40
15
15
10
15
10
75
15
2
6
5
0
+
-
-
CC
+0.55
+0.65
+0.65
+0.65
Max
0.55
0.55
1.28
70K
0.4
1.1
0.6
7.8
0.5
0.6
12
10
-
-
-
(tWR/tCK)
or tCHmin
(tRP/tCK)
(DDR333@CL=2.5)
tCLmin
-tQHS
Min
0.45
0.45
0.75
0.25
0.35
0.35
0.75
0.75
0.45
0.45
1.75
-0.6
-0.7
-0.7
-0.7
200
tHP
7.5
0.9
0.4
0.2
0.2
0.8
0.8
2.2
0.4
60
72
42
18
18
12
15
12
75
18
1
6
0
+
-
-
B3
Rev. 1.3 July 2005
Max
0.55
0.55
+0.6
+0.7
0.45
1.25
+0.7
+0.7
0.55
70K
1.1
0.6
0.6
7.8
12
12
-
-
-
DDR SDRAM
Unit
tCK
tCK
tCK
tCK
tCK
tCK
tCK
tCK
tCK
tCK
tCK
tCK
tCK
tCK
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
us
ns
ns
ns
15, 17~19
15, 17~19
16~19
16~19
20, 21
Note
j, k
j, k
22
13
11
11
18
18
14
21
21
12
23