MC9S12XDP512MAG Freescale, MC9S12XDP512MAG Datasheet - Page 1024

• Manufacturer Part Number: MC9S12XDP512MAG
• Manufacturer: Freescale

Specifications of MC9S12XDP512MAG

• Cpu Family: HCS12
• Device Core Size: 16b
• Frequency (max): 40MHz
• Interface Type: CAN/I2C/SCI/SPI
• Total Internal Ram Size: 32KB
• # I/os (max): 119
• Number Of Timers - General Purpose: 12
• Operating Supply Voltage (typ): 2.5/5V
• Operating Supply Voltage (max): 2.75/5.5V
• Operating Supply Voltage (min): 2.35/3.15V
• On-chip Adc: 2(24-chx10-bit)
• Instruction Set Architecture: CISC
• Operating Temp Range: -40C to 125C
• Operating Temperature Classification: Automotive
• Mounting: Surface Mount
• Pin Count: 144
• Package Type: LQFP
• Program Memory Type: Flash
• Program Memory Size: 512KB
• Lead Free Status / RoHS Status: Compliant

Chapter 24 DG128 Port Integration Module (S12XDG128PIMV2)
24.0.5.61 Port AD1 Data Direction Register 1 (DDR1AD1)
Read: Anytime.
Write: Anytime.
This register configures pins PAD[7:0] as either input or output.
24.0.5.62 Port AD1 Reduced Drive Register 0 (RDR0AD1)
Read: Anytime.
Write: Anytime.
This register configures the drive strength of each PAD[15:8] output pin as either full or reduced. If the
port is used as input this bit is ignored.
1026
RDR0AD1[15:8]
DDR1AD1[7:0]
Reset
Reset
Field
Field
W
W
R
7–0
R
7–0
RDR0AD115 RDR0AD114 RDR0AD113 RDR0AD112 RDR0AD111 RDR0AD110 RDR0AD19
DDR1AD17
0
0
7
7
Data Direction Port AD1 Register 1
0 Associated pin is configured as input.
1 Associated pin is configured as output.
Note: Due to internal synchronization circuits, it can take up to 2 bus clock cycles until the correct value is
Note: To use the digital input function on port AD1 the ATD1 digital input enable register (ATD1DIEN1) has
Reduced Drive Port AD1 Register 0
0 Full drive strength at output.
1 Associated pin drives at about 1/6 of the full drive strength.
DDR1AD16
read on PTAD11 register, when changing the DDR1AD1 register.
to be set to logic level “1”.
Figure 24-64. Port AD1 Reduced Drive Register 0 (RDR0AD1)
Figure 24-63. Port AD1 Data Direction Register 1 (DDR1AD1)
0
0
6
6
Table 24-55. DDR1AD1 Field Descriptions
Table 24-56. RDR0AD1 Field Descriptions
DDR1AD15
MC9S12XDP512 Data Sheet, Rev. 2.21
0
0
5
5
DDR1AD14
0
0
4
4
Description
Description
DDR1AD13
0
0
3
3
DDR1AD12
0
0
2
2
DDR1AD11
Freescale Semiconductor
0
0
1
1
DDR1AD10
RDR0AD18
0
0
0
0