MC9S12XDP512MAG Freescale, MC9S12XDP512MAG Datasheet - Page 183

• Manufacturer Part Number: MC9S12XDP512MAG
• Manufacturer: Freescale

Specifications of MC9S12XDP512MAG

• Cpu Family: HCS12
• Device Core Size: 16b
• Frequency (max): 40MHz
• Interface Type: CAN/I2C/SCI/SPI
• Total Internal Ram Size: 32KB
• # I/os (max): 119
• Number Of Timers - General Purpose: 12
• Operating Supply Voltage (typ): 2.5/5V
• Operating Supply Voltage (max): 2.75/5.5V
• Operating Supply Voltage (min): 2.35/3.15V
• On-chip Adc: 2(24-chx10-bit)
• Instruction Set Architecture: CISC
• Operating Temp Range: -40C to 125C
• Operating Temperature Classification: Automotive
• Mounting: Surface Mount
• Pin Count: 144
• Package Type: LQFP
• Program Memory Type: Flash
• Program Memory Size: 512KB
• Lead Free Status / RoHS Status: Compliant

Chapter 6
XGATE (S12XGATEV2)
6.1
The XGATE module is a peripheral co-processor that allows autonomous data transfers between the
MCU’s peripherals and the internal memories. It has a built in RISC core that is able to pre-process the
transferred data and perform complex communication protocols.
The XGATE module is intended to increase the MCU’s data throughput by lowering the S12X_CPU’s
interrupt load.
Figure 6-1
This document describes the functionality of the XGATE module, including:
6.1.1
XGATE Request
XGATE Channel
XGATE Channel ID
XGATE Channel Interrupt
XGATE Software Channel
Freescale Semiconductor
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XGATE registers
XGATE RISC core
Hardware semaphores
Interrupt handling
Debug features
Security
Instruction set
A service request from a peripheral module which is directed to the XGATE by the S12X_INT
module (see
The resources in the XGATE module (i.e. Channel ID number, Priority level, Service Request
Vector, Interrupt Flag) which are associated with a particular XGATE Request.
A 7-bit identifier associated with an XGATE channel. In S12X designs valid Channel IDs range
from $78 to $09.
An S12X_CPU interrupt that is triggered by a code sequence running on the XGATE module.
Introduction
gives an overview on the XGATE architecture.
Glossary of Terms
(Section 6.7,
Figure
(Section 6.8, “Instruction
(Section 6.6, “Debug
(Section 6.3, “Memory Map and Register
(Section 6.5,
6-1).
(Section 6.4.1, “XGATE RISC
“Security”)
(Section 6.4.4,
MC9S12XDP512 Data Sheet, Rev. 2.21
“Interrupts”)
Mode”)
“Semaphores”)
Set”)
Core”)
Definition”)
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