MC9S12XDP512MAG Freescale, MC9S12XDP512MAG Datasheet - Page 213

• Manufacturer Part Number: MC9S12XDP512MAG
• Manufacturer: Freescale

Specifications of MC9S12XDP512MAG

• Cpu Family: HCS12
• Device Core Size: 16b
• Frequency (max): 40MHz
• Interface Type: CAN/I2C/SCI/SPI
• Total Internal Ram Size: 32KB
• # I/os (max): 119
• Number Of Timers - General Purpose: 12
• Operating Supply Voltage (typ): 2.5/5V
• Operating Supply Voltage (max): 2.75/5.5V
• Operating Supply Voltage (min): 2.35/3.15V
• On-chip Adc: 2(24-chx10-bit)
• Instruction Set Architecture: CISC
• Operating Temp Range: -40C to 125C
• Operating Temperature Classification: Automotive
• Mounting: Surface Mount
• Pin Count: 144
• Package Type: LQFP
• Program Memory Type: Flash
• Program Memory Size: 512KB
• Lead Free Status / RoHS Status: Compliant

6.8.2.2
All logic and arithmetic instructions support the 8 bit immediate addressing mode (IMM8: RD = RD
#IMM8) and the triadic addressing mode (TRI: RD = RS1 RS2).
All arithmetic is considered as signed, sign, overflow, zero and carry flag will be updated. The carry will
not be affected for logical operations.
6.8.2.3
This group comprises transfers from and to some special registers
Branch Instructions
The branch offset is +255 words or -256 words counted from the beginning of the next instruction. Since
instructions have a fixed 16 bit width, the branch offsets are word aligned by shifting the offset value by 2.
An unconditional branch allows a +511 words or -512 words branch distance.
6.8.2.4
Shift operations allow the use of a 4 bit wide immediate value to identify a shift width within a 16 bit word.
For shift operations a value of 0 does not shift at all, while a value of 15 shifts the register RD by 15 bits.
In a second form the shift value is contained in the bits 3:0 of the register RS.
Examples:
Freescale Semiconductor
ADDL
ANDH
ADD
SUB
AND
OR
TFR
BEQ
BRA
LSL
LSR
ASR
Logic and Arithmetic Instructions
Register – Register Transfers
Shift Instructions
R2,#1
R4,#$FE
R3,R4,R5
R3,R4,R5
R3,R4,R5
R3,R4,R5
R3,CCR
label
label
R4,#1
R4,#3
R4,R2
; R4 = R4 << 1; shift register R4 by 1 bit to the left
; R4 = R4 >> 3; shift register R4 by 3 bits to the right
; R4 = R4 >> R2;arithmetic shift register R4 right by the amount
;
MC9S12XDP512 Data Sheet, Rev. 2.21
; increment R2
; R4.H = R4.H & $FE, clear lower bit of higher byte
; R3 = R4 + R5
; R3 = R4 - R5
; R3 = R4 & R5 logical AND on the whole word
; R3 = R4 | R5
; transfers the condition code register to the low byte of
; register R3
; if Z flag = 1 branch to label
of bits contained in R2[3:0].
Chapter 6 XGATE (S12XGATEV2)
213