MC9S12XDP512MAG Freescale, MC9S12XDP512MAG Datasheet - Page 56

• Manufacturer Part Number: MC9S12XDP512MAG
• Manufacturer: Freescale

Specifications of MC9S12XDP512MAG

• Cpu Family: HCS12
• Device Core Size: 16b
• Frequency (max): 40MHz
• Interface Type: CAN/I2C/SCI/SPI
• Total Internal Ram Size: 32KB
• # I/os (max): 119
• Number Of Timers - General Purpose: 12
• Operating Supply Voltage (typ): 2.5/5V
• Operating Supply Voltage (max): 2.75/5.5V
• Operating Supply Voltage (min): 2.35/3.15V
• On-chip Adc: 2(24-chx10-bit)
• Instruction Set Architecture: CISC
• Operating Temp Range: -40C to 125C
• Operating Temperature Classification: Automotive
• Mounting: Surface Mount
• Pin Count: 144
• Package Type: LQFP
• Program Memory Type: Flash
• Program Memory Size: 512KB
• Lead Free Status / RoHS Status: Compliant

Chapter 1 Device Overview MC9S12XD-Family
1.2.3.3
This input only pin is reserved for test. This pin has a pulldown device.
1.2.3.4
This input only pin enables or disables the on-chip voltage regulator. The input has a pullup device.
1.2.3.5
Please ask your Freescale representative for the interactive application note to compute PLL loop filter
elements. Any current leakage on this pin must be avoided.
1.2.3.6
The BKGD/MODC pin is used as a pseudo-open-drain pin for the background debug communication. It
is used as a MCU operating mode select pin during reset. The state of this pin is latched to the MODC bit
at the rising edge of RESET. The BKGD pin has a pullup device.
1.2.3.7
PAD[23:8] are general-purpose input or output pins and analog inputs AN[23:8] of the analog-to-digital
converter ATD1.
1.2.3.8
PAD[7:0] are general-purpose input or output pins and analog inputs AN[7:0] of the analog-to-digital
converter ATD0.
1.2.3.9
PAD[15:0] are general-purpose input or output pins and analog inputs AN[15:0] of the analog-to-digital
converter ATD1.
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TEST — Test Pin
VREGEN — Voltage Regulator Enable Pin
XFC — PLL Loop Filter Pin
BKGD / MODC — Background Debug and Mode Pin
PAD[23:8] / AN[23:8] — Port AD Input Pins of ATD1
PAD[7:0] / AN[7:0] — Port AD Input Pins of ATD0
PAD[15:0] / AN[15:0] — Port AD Input Pins of ATD1
The TEST pin must be tied to V
Figure 1-10. PLL Loop Filter Connections
MCU
MC9S12XDP512 Data Sheet, Rev. 2.21
XFC
SS
NOTE
V
in all applications.
DDPLL
R
C
0
S
V
DDPLL
C
P
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