MC9S12XDP512MAG Freescale, MC9S12XDP512MAG Datasheet - Page 965

• Manufacturer Part Number: MC9S12XDP512MAG
• Manufacturer: Freescale

Specifications of MC9S12XDP512MAG

• Cpu Family: HCS12
• Device Core Size: 16b
• Frequency (max): 40MHz
• Interface Type: CAN/I2C/SCI/SPI
• Total Internal Ram Size: 32KB
• # I/os (max): 119
• Number Of Timers - General Purpose: 12
• Operating Supply Voltage (typ): 2.5/5V
• Operating Supply Voltage (max): 2.75/5.5V
• Operating Supply Voltage (min): 2.35/3.15V
• On-chip Adc: 2(24-chx10-bit)
• Instruction Set Architecture: CISC
• Operating Temp Range: -40C to 125C
• Operating Temperature Classification: Automotive
• Mounting: Surface Mount
• Pin Count: 144
• Package Type: LQFP
• Program Memory Type: Flash
• Program Memory Size: 512KB
• Lead Free Status / RoHS Status: Compliant

23.0.7.8
This port is associated with the CAN40 and SPI0. Port M pins PM[7:0] can be used for either
general purpose I/O, or with the CAN, SCI and SPI subsystems.
The CAN0, CAN4 and SPI0 pins can be re-routed. Refer to
Register
23.0.7.9
This port is associated with the PWM, SPI1 and SPI2. Port P pins PP[7:0] can be used for either
general purpose I/O, or with the PWM and SPI subsystems.
The pins are shared between the PWM channels and the SPI1 and SPI2. If the PWM is enabled the
pins become PWM output channels with the exception of pin 7 which can be PWM input or output.
If SPI1 or SPI2 are enabled and PWM is disabled, the respective pin configuration is determined
by status bits in the SPI.
The SPI1 and SPI2 pins can be re-routed. Refer to
(MODRR)”.
Port P offers 8 I/O pins with edge triggered interrupt capability in wired-OR fashion
(Section 23.0.8, “Pin
23.0.7.10 Port H
This port is associated with the SPI1, SPI2, SCI4. Port H pins PH[7:0] can be used for either
general purpose I/O, or with the SPI and SCI subsystems. Port H pins can be used with the routed
SPI1 and SPI2. Refer to
Port H offers 8 I/O pins with edge triggered interrupt capability
23.0.7.11 Port J
This port is associated with the chip selects CS0, CS1, CS2 and CS3 as well as with CAN4, CAN0,
IIC1, IIC0, and SCI2. Port J pins PJ[7:4] and PJ[2:0] can be used for either general purpose I/O, or
with the CAN, IIC, or SCI subsystems. If IIC takes precedence the associated pins become IIC
(MODRR)”.
Port M
Port P
PS[7:4] are not available in 80-pin packages.
PM[7:6] are not available in 80-pin packages.
PP[6] is not available in 80-pin packages.
Port H is not available in 80-pin packages.
Interrupts”).
Section 23.0.5.37, “Module Routing Register
NOTE
NOTE
NOTE
NOTE
Section 23.0.5.37, “Module Routing Register
Section 23.0.5.37, “Module Routing
(Section 23.0.8, “Pin
(MODRR)”.
Interrupts”).