MC9S12XDP512MAG Freescale, MC9S12XDP512MAG Datasheet - Page 1156

• Manufacturer Part Number: MC9S12XDP512MAG
• Manufacturer: Freescale

Specifications of MC9S12XDP512MAG

• Cpu Family: HCS12
• Device Core Size: 16b
• Frequency (max): 40MHz
• Interface Type: CAN/I2C/SCI/SPI
• Total Internal Ram Size: 32KB
• # I/os (max): 119
• Number Of Timers - General Purpose: 12
• Operating Supply Voltage (typ): 2.5/5V
• Operating Supply Voltage (max): 2.75/5.5V
• Operating Supply Voltage (min): 2.35/3.15V
• On-chip Adc: 2(24-chx10-bit)
• Instruction Set Architecture: CISC
• Operating Temp Range: -40C to 125C
• Operating Temperature Classification: Automotive
• Mounting: Surface Mount
• Pin Count: 144
• Package Type: LQFP
• Program Memory Type: Flash
• Program Memory Size: 512KB
• Lead Free Status / RoHS Status: Compliant

Chapter 28 256 Kbyte Flash Module (S12XFTX256K2V1)
All bits in the FPROT register are readable and writable with restrictions (see
Protection
During the reset sequence, the FPROT register is loaded from the Flash Configuration Field at global
address 0x7F_FF0D. To change the Flash protection that will be loaded during the reset sequence, the
upper sector of the Flash memory must be unprotected, then the Flash Protect/Security byte located as
described in
Trying to alter data in any protected area in the Flash memory will result in a protection violation error and
the PVIOL flag will be set in the FSTAT register. The mass erase of a Flash block is not possible if any of
the Flash sectors contained in the Flash block are protected.
1158
FPHS[1:0]
FPLS[1:0]
FPOPEN
FPHDIS
FPLDIS
Reset
RNV6
Field
4:3
1:0
7
6
5
2
W
R
FPOPEN
Restrictions”) except for RNV[6] which is only readable.
Flash Protection Open — The FPOPEN bit determines the protection function for program or erase as shown
in
0 The FPHDIS and FPLDIS bits define unprotected address ranges as specified by the corresponding
1 The FPHDIS and FPLDIS bits enable protection for the address range specified by the corresponding
Reserved Nonvolatile Bit — The RNV[6] bit should remain in the erased state for future enhancements.
Flash Protection Higher Address Range Disable — The FPHDIS bit determines whether there is a
protected/unprotected area in a specific region of the Flash memory ending with global address 0x7F_FFFF.
0 Protection/Unprotection enabled.
1 Protection/Unprotection disabled.
Flash Protection Higher Address Size — The FPHS[1:0] bits determine the size of the protected/unprotected
area as shown
Flash Protection Lower Address Range Disable — The FPLDIS bit determines whether there is a
protected/unprotected area in a specific region of the Flash memory beginning with global address 0x7F_8000.
0 Protection/Unprotection enabled.
1 Protection/Unprotection disabled.
Flash Protection Lower Address Size — The FPLS[1:0] bits determine the size of the protected/unprotected
area as shown in
Table 28-1
F
7
Table
FPHS[1:0] and FPLS[1:0] bits. For an MCU without an EEPROM module, the FPOPEN clear state allows the
main part of the Flash block to be protected while a small address range can remain unprotected for EEPROM
emulation.
FPHS[1:0] and FPLS[1:0] bits.
28-10.
= Unimplemented or Reserved
RNV6
must be reprogrammed.
inTable
F
6
Table
Figure 28-10. Flash Protection Register (FPROT)
28-11. The FPHS[1:0] bits can only be written to while the FPHDIS bit is set.
28-12. The FPLS[1:0] bits can only be written to while the FPLDIS bit is set.
Table 28-9. FPROT Field Descriptions
FPHDIS
MC9S12XDP512 Data Sheet, Rev. 2.21
F
5
F
4
Description
FPHS
F
3
FPLDIS
F
2
Section 28.3.2.5.1, “Flash
Freescale Semiconductor
F
1
FPLS
F
0