AMD-K6-IIIE+550ACR AMD (ADVANCED MICRO DEVICES), AMD-K6-IIIE+550ACR Datasheet - Page 122

• Manufacturer Part Number: AMD-K6-IIIE+550ACR
• Manufacturer: AMD (ADVANCED MICRO DEVICES)

Specifications of AMD-K6-IIIE+550ACR

• Lead Free Status / RoHS Status: Not Compliant

AMD-K6™-IIIE+ Embedded Processor Data Sheet
5.9
Pin Attribute
Summary
Driven and Floated
100
BE[7:0]# (Byte Enables)
Output
BE[7:0]# are used by the processor to indicate the valid data
bytes during a write cycle and the requested data bytes during
a read cycle. The byte enables can be used to derive address bits
A[2:0], which are not physically part of the processor’s address
bus. The processor checks and generates valid data parity for
the data bytes that are valid as defined by the byte enables. The
eight byte enables correspond to the eight bytes of the data bus
as follows:
The processor expects data to be driven by the system logic on
all eight bytes of the data bus during a burst cache-line read
cycle, independent of the byte enables that are asserted.
The byte enables are also used to distinguish between special
bus cycles as defined in Table 24 on page 142.
BE[7:0]# are driven off the same clock edge as ADS # and
remain in the same state until the clock edge on which NA# or
the last expected BRDY # of the cycle is sampled asserted.
BE[7:0]# are driven during memory cycles, I/O cycles, special
bus cycles, and interrupt acknowledge cycles.
The processor floats BE[7:0]# off the clock edge that BOFF# is
sampled asserted and off the clock edge that the processor
asserts HLDA in recognition of HOLD. Unlike the address bus,
BE[7:0]# are not floated in response to AHOLD.
BE7#: D[63:56]
BE6#: D[55:48]
BE5#: D[47:40]
BE4#: D[39:32]
Preliminary Information
Signal Descriptions
BE3#: D[31:24]
BE2#: D[23:16]
BE1#: D[15:8]
BE0#: D[7:0]
23543A/0—September 2000
Chapter 5