AMD-K6-IIIE+550ACR AMD (ADVANCED MICRO DEVICES), AMD-K6-IIIE+550ACR Datasheet - Page 237

• Manufacturer Part Number: AMD-K6-IIIE+550ACR
• Manufacturer: AMD (ADVANCED MICRO DEVICES)

Specifications of AMD-K6-IIIE+550ACR

• Lead Free Status / RoHS Status: Not Compliant

23543A/0—September 2000
9.8
Chapter 9
Write Allocate
L1 instruction-cache lines and L2 cache lines are replaced using
a Least Recently Used (LRU) algorithm. If a line replacement is
required, lines are replaced when read cache misses occur.
The L1 data cache uses a slightly different approach to line
replacement. If a miss occurs, and a replacement is required,
lines are replaced by using a Least Recently Allocated (LRA)
algorithm.
Write allocate, if enabled, occurs when the processor has a
pending memory write cycle to a cacheable line and the line
does not currently reside in the L1 data cache. If the line does
not exist in the L2 cache, the processor performs a 32-byte burst
read cycle on the system bus to fetch the data-cache line
addressed by the pending write cycle. If the line does exist in
the L2 cache, the data is supplied directly from the L2 cache, in
which case a system bus cycle is not executed. The data
associated with the pending write cycle is merged with the
recently-allocated data-cache line and stored in the processor’s
L1 data cache. If the data-cache line was fetched from memory
(because of a L2 cache miss), the data is stored, without
modification, in the L2 cache. The final MESI state of the cache
lines depends on the state of the WB/WT# and PWT signals
during the burst read cycle and the subsequent L1 data cache
write hit (See Table 39 on page 221 to determine the cache-line
states and the access types following a cache write miss). If the
L1 data cache line is stored in the modified state, then the same
cache line is stored in the L2 cache in the exclusive state. If the
L1 data cache line is stored in the shared state, then the same
cache line is stored in the L2 cache in the shared state.
If a data-cache line fetch from memory is attempted because
the write allocate misses the L2 cache, and KEN# is sampled
negated, the processor does not perform an allocation. In this
case, the pending write cycle is executed as a single write cycle
on the system bus.
During write allocates that miss the L2 cache, a 32-byte burst
read cycle is executed in place of a non-burst write cycle. While
the burst read cycle generally takes longer to execute than the
non-burst write cycle, performance gains are realized on
subsequent write cycle hits to the write-allocated cache line.
Cache Organization
AMD-K6™-IIIE+ Embedded Processor Data Sheet
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