AMD-K6-IIIE+550ACR AMD (ADVANCED MICRO DEVICES), AMD-K6-IIIE+550ACR Datasheet - Page 255

• Manufacturer Part Number: AMD-K6-IIIE+550ACR
• Manufacturer: AMD (ADVANCED MICRO DEVICES)

Specifications of AMD-K6-IIIE+550ACR

• Lead Free Status / RoHS Status: Not Compliant

23543A/0—September 2000
10.3
Chapter 10
Memory-Range Restrictions
WCn (n=0, 1). When set to 1, this memory range is defined as
write combinable (see Table 43). Write-combinable memory is
uncacheable.
UCn (n=0, 1). When set to 1, this memory range is defined as
uncacheable (see Table 43).
Table 43. WC/UC Memory Type
The following rules regarding the address alignment and size of
each range must be adhered to when programming the physical
base address and physical address mask fields of the UWCCR
register:
The minimum size of each range is 128 Kbytes.
The physical base address must be aligned on a 128-Kbyte
boundary.
The physical base address must be range-size aligned. For
example, if the size of the range is 1 Mbyte, then the
physical base address must be aligned on a 1-Mbyte
boundary.
All bits set to 1 in the physical address mask must be
contiguous. Likewise, all bits set to 0 in the physical address
mask must be contiguous. For example:
111_1111_1100_0000b is a valid physical address mask.
111_1111_1101_0000b is invalid.
0 or 1
WCn
0
1
Write Merge Buffer
UCn
0
0
1
AMD-K6™-IIIE+ Embedded Processor Data Sheet
Memory Type
No effect on cacheability or write combining
Write-combining memory range (uncacheable)
Uncacheable memory range
233