AMD-K6-IIIE+550ACR AMD (ADVANCED MICRO DEVICES), AMD-K6-IIIE+550ACR Datasheet - Page 221

• Manufacturer Part Number: AMD-K6-IIIE+550ACR
• Manufacturer: AMD (ADVANCED MICRO DEVICES)

Specifications of AMD-K6-IIIE+550ACR

• Lead Free Status / RoHS Status: Not Compliant

23543A/0—September 2000
8
8.1
FLUSH#
BF[2:0]
Chapter 8
Power-on Configuration and Initialization
Signals Sampled During the Falling Transition of RESET
On power-on the system logic must reset the AMD-K6-IIIE+
processor by asserting the RESET signal. When the processor
samples RESET asserted, it immediately flushes and initializes
all internal resources and its internal state, including its
pipelines and caches, the floating-point state, the MMX and
3DNow! states, and all registers. Then the processor jumps to
address FFFF_FFF0h to start instruction execution.
FLUSH# is sampled on the falling transition of RESET to
determine if the processor begins normal instruction execution
or enters Three-State Test mode.
The in t er n a l op erat i n g f re q u e n cy o f t h e p roc e s so r is
determined by the state of the bus frequency signals BF[2:0]
when they are sampled during the falling transition of RESET.
The frequency of the CLK input signal is multiplied internally
by a ratio defined by BF[2:0]. (See “BF[2:0] (Bus Frequency)”
on page 101 for the processor-clock to bus-clock ratios.)
If FLUSH# is High during the falling transition of RESET,
the processor unconditionally runs its Built-In Self Test
(BIST), performs the normal reset functions, then jumps to
address FFFF_FFF0h to start instruction execution. (See
“Built-In Self-Test (BIST)” on page 251 for more details.)
If FLUSH# is Low during the falling transition of RESET,
the
“Three-State Test Mode” on page 252 and “FLUSH# (Cache
Flush)” on page 112 for more details.)
Power-on Configuration and Initialization
processor
enters
AMD-K6™-IIIE+ Embedded Processor Data Sheet
Three-State
Test
mode.
(See
199