AMD-K6-IIIE+550ACR AMD (ADVANCED MICRO DEVICES), AMD-K6-IIIE+550ACR Datasheet - Page 246

• Manufacturer Part Number: AMD-K6-IIIE+550ACR
• Manufacturer: AMD (ADVANCED MICRO DEVICES)

Specifications of AMD-K6-IIIE+550ACR

• Lead Free Status / RoHS Status: Not Compliant

AMD-K6™-IIIE+ Embedded Processor Data Sheet
Figure 86. Page Flush/Invalidate Register (PFIR)
WBINVD and INVD
Cache-Line
Replacement
224
Symbol
63
LINPAGE
PF
F/I
20-bit Linear Page Address
Page Fault Occurred
Flush/Invalidate Command
Reserved
Description
LINPAGE Field. This 20-bit field must be written with bits 31:12 of
the linear address of the 4-Kbyte page that is to be invalidated
and optionally flushed from the L1 or the L2 cache.
PF Bit. If an attempt to invalidate or flush a page results in a
page fault, the processor sets the PF bit to 1, and the invalidate
or flush operation is not performed (even though invalidate
operations do not normally generate page faults). In this case,
an actual page fault exception is not generated. If the PF bit
equals 0 after an invalidate or flush operation, then the
operation executed successfully. The PF bit must be read after
every write to the PFIR register to determine if the invalidate
or flush operation executed successfully.
F/I Bit. This bit is used to control the type of action that occurs to
the specified linear page. If a 0 is written to this bit, the
operation is a flush, in which case all cache lines in the
modified state within the specified page are written back to
memory, after which the entire page is invalidated. If a 1 is
written to this bit, the operation is an invalidation, in which
case the entire page is invalidated without the occurrence of
any writebacks.
These x86 instructions cause all cache lines to be marked as
invalid. WBINVD writes back modified lines before marking all
cache lines invalid. INVD does not write back modified lines.
Replacing lines in the L1 cache and the L2 cache, according to
the line replacement algorithms described in “Cache-Line
Fills” on page 213, ensures coherency between external
memory and the caches.
Bit
31-12
8
0
Preliminary Information
Cache Organization
32
31
LINPAGE
12
11
9 8 7
23543A/0—September 2000
P
F
1 0
Chapter 9
F
/
I