AMD-K6-IIIE+550ACR AMD (ADVANCED MICRO DEVICES), AMD-K6-IIIE+550ACR Datasheet - Page 296

• Manufacturer Part Number: AMD-K6-IIIE+550ACR
• Manufacturer: AMD (ADVANCED MICRO DEVICES)

Specifications of AMD-K6-IIIE+550ACR

• Lead Free Status / RoHS Status: Not Compliant

AMD-K6™-IIIE+ Embedded Processor Data Sheet
Debug Exceptions
274
The LE (bit 8) and GE (bit 9) bits in DR7 have no effect on the
operation of the processor and are provided in order to be
software-compatible with previous generations of x86
processors.
When set to 1, the GD bit in DR7 (bit 13) enables the debug
exception associated with the BD bit (bit 13) in DR6. This bit is
set to 0 when a debug exception is generated.
LEN3–LEN0 and RW3–RW0 are two-bit fields in DR7 that
specify the length and type of each breakpoint as defined in
Table 54.
Table 54. DR7 LEN and RW Definitions
Notes:
1. LEN bits equal to 10b is undefined.
2. When RW equals 00b, LEN must be equal to 00b.
3. When RW equals 10b, debugging extensions (DE) must be enabled (bit 3 of CR4 must be set to 1).
A debug exception is categorized as either a debug trap or a
debug fault.
All debug traps and faults generate either an Interrupt 01h or
an Interrupt 03h exception.
If DE is set to 0, then RW equal to 10b is undefined.
A debug trap calls the debugger following the execution of
the instruction that caused the trap.
A debug fault calls the debugger prior to the execution of the
instruction that caused the fault.
LEN Bits
00b
00b
01b
11b
00b
01b
11b
00b
01b
11b
Preliminary Information
1
Test and Debug
RW Bits
00b
10b
01b
11b
3
2
Breakpoint
Instruction Execution
One-byte Data Write
Two-byte Data Write
Four-byte Data Write
One-byte I/O Read or Write
Two-byte I/O Read or Write
Four-byte I/O Read or Write
One-byte Data Read or Write
Two-byte Data Read or Write
Four-byte Data Read or Write
23543A/0—September 2000
Chapter 13