AMD-K6-IIIE+550ACR AMD (ADVANCED MICRO DEVICES), AMD-K6-IIIE+550ACR Datasheet - Page 215

• Manufacturer Part Number: AMD-K6-IIIE+550ACR
• Manufacturer: AMD (ADVANCED MICRO DEVICES)

Specifications of AMD-K6-IIIE+550ACR

• Lead Free Status / RoHS Status: Not Compliant

23543A/0—September 2000
Stop Grant and Stop
Clock States
Chapter 7
Figure 79 on page 194 and Figure 80 on page 195 show the
processor transition from normal execution to the Stop Grant
state, then to the Stop Clock state, back to the Stop Grant state,
and finally back to normal execution. The series of transitions
begins when the processor samples STPCLK# asserted. On
recognizing a STPCLK# interrupt at the next instruction
retirement boundary, the processor performs the following
actions, in the order shown:
1. Its instruction pipelines are flushed.
2. All pending and in-progress bus cycles are completed.
3. The STPCLK# assertion is acknowledged by executing a
4. Its internal clock is stopped after BRDY# of the Stop Grant
5. The Stop Clock state is entered if the system logic stops the
STPCLK# is sampled as a level-sensitive input on every clock
edge but is not recognized until the next instruction boundary.
The system logic drives the signal either synchronously or
asynchronously. If it is asserted asynchronously, it must be
asserted for a minimum pulse width of two clocks. STPCLK#
must remain asserted until recognized, which is indicated by
the completion of the Stop Grant special cycle.
Stop Grant special bus cycle.
special bus cycle is sampled asserted (if EWBE# is masked
off, then entry into the Stop Grant state is not affected by
EWBE#) and after EWBE# is sampled asserted.
bus clock CLK (optional).
Bus Cycles
AMD-K6™-IIIE+ Embedded Processor Data Sheet
193