PCF8591P NXP Semiconductors, PCF8591P Datasheet - Page 14

• Manufacturer Part Number: PCF8591P
• Description: IC, A/D AND D/A CONVERTER, 8BIT, 16-DIP
• Manufacturer: NXP Semiconductors
• Type: General Purposer

Specifications of PCF8591P

• Number Of Channels: 1
• Number Of Adc's: 1
• Number Of Dac's: 1
• Adc/dac Resolution: 8b
• Interface Type: Serial (I2C)
• Operating Supply Voltage (typ): 3.3/5V
• Sample Rate: 11.1KSPS
• Number Of Adc Inputs: 4
• Number Of Dac Outputs: 1
• Operating Supply Voltage (max): 6V
• Operating Supply Voltage (min): 2.5V
• Operating Temperature (max): 85C
• Operating Temperature (min): -40C
• Pin Count: 16
• Mounting: Through Hole
• Supply Voltage Range: 2.5V To 6V
• Operating Temperature Range: -40°C To +85°C
• Digital Ic Case Style: DIP
• No. Of Pins: 16
• Linearity Error -: 1.5LSB
• Termination Type: DIP
• Supply Voltage Max: 8V
• Input Channels Per Adc: 1
• Rohs Compliant: Yes
• Filter Terminals: DIP
• Conversion Time: 90µs
• Data Interface: I2C, Serial
• Lead Free Status / RoHS Status: Compliant

Philips Semiconductors
8.3
A device generating a message is a ‘transmitter’, a device receiving a message is the ‘receiver’. The device that controls
the message is the ‘master’ and the devices which are controlled by the master are the ‘slaves’.
8.4
The number of data bytes transferred between the start and stop conditions from transmitter to receiver is not limited.
Each data byte of eight bits is followed by one acknowledge bit. The acknowledge bit is a HIGH level put on the bus by
the transmitter whereas the master also generates an extra acknowledge related clock pulse. A slave receiver which is
addressed must generate an acknowledge after the reception of each byte. Also a master must generate an
acknowledge after the reception of each byte that has been clocked out of the slave transmitter. The device that
acknowledges has to pull down the SDA line during the acknowledge clock pulse, so that the SDA line is stable LOW
during the HIGH period of the acknowledge related clock pulse. A master receiver must signal an end of data to the
transmitter by not generating an acknowledge on the last byte that has been clocked out of the slave. In this event the
transmitter must leave the data line HIGH to enable the master to generate a stop condition.
1998 Jul 02
8-bit A/D and D/A converter
handbook, full pagewidth
System configuration
Acknowledge
SDA
SCL
TRANSMITTER /
RECEIVER
MASTER
BY TRANSMITTER
DATA OUTPUT
DATA OUTPUT
BY RECEIVER
SCL FROM
MASTER
RECEIVER
condition
Fig.14 Acknowledgement on the I
START
SLAVE
S
Fig.13 System configuration.
1
TRANSMITTER /
RECEIVER
14
SLAVE
2
2
C-bus.
TRANSMITTER
MASTER
not acknowledge
acknowledge
8
acknowledgement
clock pulse for
TRANSMITTER /
RECEIVER
MASTER
9
Product specification
MBC602
PCF8591
MBA605