IDT5V9885CPFI IDT, Integrated Device Technology Inc, IDT5V9885CPFI Datasheet - Page 10

• Manufacturer Part Number: IDT5V9885CPFI
• Description: IC CLK GEN 3.3V EEPROM 32-TQFP
• Manufacturer: IDT, Integrated Device Technology Inc
• Type: Clock Generatorr

Specifications of IDT5V9885CPFI

• Pll: Yes with Bypass
• Input: LVCMOS, LVTTL, Crystal
• Output: LVCMOS, LVDS, LVPECL, LVTTL
• Number Of Circuits: 1
• Ratio - Input:output: 2:8
• Differential - Input:output: No/Yes
• Frequency - Max: 500MHz
• Divider/multiplier: Yes/Yes
• Voltage - Supply: 3.135 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 32-TQFP, 32-VQFP
• Frequency-max: 500MHz
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 5V9885CPFI

the VCO. Start with D = 1, using Eq.10 and Eq.11.
to enhance the profile of the spread spectrum waveform.
samples must not exceed 63 with SS_OFFSET set to '0', 61 or 62 is well within the limits. It is the discretion of the user to define the shape of the profile that
is better suited for the intended application.
The PLL loop bandwidth must be at least 10x the modulation frequency along with higher damping (larger ω uz) to prevent the spread spectrum from being filtered
and reduce extraneous noise. Refer to the LOOP FILTER section for more detail on ω uz. The A[3:0] must be used for spread spectrum, even if the total multiplier
value is an even integer.
FRACTIONAL DIVIDER
SS_OFFSET bits would determine the fractional divide value. See the SPREAD SPECTRUM GENERATION section for more details on the TSSC, SD, and
SS_OFFSET bits. The following equation governs how the fractional divide value is set.
IDT5V9885C
3.3V EEPROM PROGRAMMABLE CLOCK GENERATOR
Example
F
Since the spread is center, the SS_OFFSET can be set to '0'. Solve for the nominal M value; keep in mind that the nominal M should be chosen to maximize
M
Using Eq.4, we arbitrarily choose N = 22, A = 3. Now that we have the nominal M value, we can determine TSSC and NSSC by using Eq.12.
Nssc * Tssc = 25MHz / (33KHz * 4) = 190
However, using Eq. 7 and Eq.8, we find that the closest value is when TSSC = 14 and NSSC = 6. Keep in mind to maximize the number of samples used
Tssc = 14 + 2 = 16
Nssc = 6 * 2 = 12
Nssc * Tssc = 192
Use Eq.14 to determine the value of the sigma-delta-encoded samples.
±2% = Σ∆ * 100
Σ∆ = 61.44
Either round up or down to the nearest integer value. Therefore, we end up with 61 or 62 for sigma-delta-encoded samples. Since the sigma-delta-encoded
Using Eq.14 again, the actual spread for the sigma-delta-encoded samples of 61 and 62 are ±1.99% and ±2.02%, respectively.
Use Eq.10 to determine if the X2 bit needs to be set;
Amplitude = 48 * (1.99 or 2.02) / 100 = 0.48 < 1
Therefore, the X2 = '0 '. The dither bit is left to the discretion of the user.
The example above was of a center spread using spread spectrum. For down spread, the nominal M value can be set one integer value lower to 43.
Note that the 5V9885C should not be programmed with TSSC > '0', SS_OFFSET = '0', and SD = '0' in order to prevent an unstable state in the modulator.
There is the option for the feedback-divider to be programmed as a fractional divider for only PLL0 and PLL. By setting TSSC > '0' and SD bits to '0', the
M = 2*N[11:0] + A[3:0] + 1 + SS_OFFSET[5:0] *1/64
IN
NOM
= 25MHz, F
= 1200MHz / 25MHz = 48
64 * 48
OUT
= 100MHz, Fssc = 33KHz with center spread of ±2%. Find the necessary spread spectrum register settings.
2
10
INDUSTRIAL TEMPERATURE RANGE