IDT5V9885CPFI IDT, Integrated Device Technology Inc, IDT5V9885CPFI Datasheet - Page 32

• Manufacturer Part Number: IDT5V9885CPFI
• Description: IC CLK GEN 3.3V EEPROM 32-TQFP
• Manufacturer: IDT, Integrated Device Technology Inc
• Type: Clock Generatorr

Specifications of IDT5V9885CPFI

• Pll: Yes with Bypass
• Input: LVCMOS, LVTTL, Crystal
• Output: LVCMOS, LVDS, LVPECL, LVTTL
• Number Of Circuits: 1
• Ratio - Input:output: 2:8
• Differential - Input:output: No/Yes
• Frequency - Max: 500MHz
• Divider/multiplier: Yes/Yes
• Voltage - Supply: 3.135 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 32-TQFP, 32-VQFP
• Frequency-max: 500MHz
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 5V9885CPFI

RAM (PROGRAMMING REGISTER) TABLES
IDT5V9885C
3.3V EEPROM PROGRAMMABLE CLOCK GENERATOR
ADDR
0x0A
0x0B
0x0C
0x0D
0x0E
0x0F
0x1A
0x1B
0x1C
0x1D
0x1E
0x00
0x01
0x02
0x03
0x04
0x05
0x06
0x07
0x08
0x09
0x10
0x11
0x12
0x13
0x14
0x15
0x16
0x17
0x18
0x19
7
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
6
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
5
0
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
4
0
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
BIT #
3
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
2
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Hex Value
Register
00
FF
30
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
40
00
ODIV0_CONFIG0
ODIV0_CONFIG1
ODIV0_CONFIG2
ODIV0_CONFIG3
SP
7
CP0[3:0]_CONFIG0
CP0[3:0]_CONFIG1
CP0[3:0]_CONFIG2
CP0[3:0]_CONFIG3
A0[3:0]_CONFIG0
A0[3:0]_CONFIG1
A0[3:0]_CONFIG2
A0[3:0]_CONFIG3
OKC
SH
6
IP0[2:0]_CONFIG0
IP0[2:0]_CONFIG1
IP0[2:0]_CONFIG2
IP0[2:0]_CONFIG3
GINEN5
OE6
OS6
5
XDRV[1:0]
Rese rved
D0 [7:0]_CONFIG0
D0 [7:0]_CONFIG1
D0 [7:0]_CONFIG2
D0 [7:0]_CONFIG3
N0 [7:0]_CONFIG0
N0 [7:0]_CONFIG1
N0 [7:0]_CONFIG2
N0 [7:0]_CONFIG3
GINEN4
XTALCAP[7:0]
OE5
OS5
4
BIT #
GINE N3
OE4
OS4
3
GINEN2
PLLS2
RZ0[3:0]_CONFIG0
RZ0[3:0]_CONFIG1
RZ0[3:0]_CONFIG2
RZ0[3:0]_CONFIG3
CZ0[3:0]_CONFIG0
CZ0[3:0]_CONFIG1
CZ0[3:0]_CONFIG2
CZ0[3:0]_CONFIG3
N0[11:8]_CONFIG0
N0[11:8]_CONFIG1
N0[11:8]_CONFIG2
N0[11:8]_CONFIG3
OE3
OS3
2
32
GINEN1
PLLS1
OE 2
OS 2
1
GINEN0
PLLS0
MFC
OE1
OS1
0
MFC=Manual Frequency Control Mode ('0'=All PLL Control (Default), "1"=PLL0 Control Only );
GINEN0 to GINEN5=GINx Pins Enable Bits, ("1"=Enable (Default), "0"=No Connect (Internal State will be "Low"));
XDRV=crystal drive strength ("00" = 1.4V, "01" = 2.3V, "10"= 3.2V pk-pk swing typical, "11"=XTA L_IN with external clock-default); When
"11", XTA LCAP[7:0] value must also be set to "0".
B its 7,6, 3, 2, 1, 0 are reserved and should be set to "0"
XTAL load cap = 3.5pF+ (0.125 x XTALCAP[7:0]) , 3.5pF to 35.4pF; Each XTAL pin to GND;
(For example, "00000001"=0.125pF, "00000010"=0.25pF, "00000100"=0.5pF); Default = "00000000";
P LL0 LOOP FILTER SETTING
ODIV0_CONFIGx=Determines which one of the 2 "Qx-Divider" Configurations to use wi
P LL0 INPUT DIVIDER D0 SE TTING
MFC=Manual Frequency Control Mode ('0'=All PLL Control (Default), "1"=PLL0 Control Only );
GINEN0 to GINEN5=GINx Pins Enable Bits, ("1"=Enable (Default), "0"=No Connect (Internal State w ill be "Low "));
XDRV=crystal drive strength ("00" = 1.4V, "01" = 2.3V, "10"= 3.2V pk-pk swing typical, "11"=XTAL_IN with external clock-
default); When "11", XTALCAP[7:0] value must also be set to "0".
Bits 7,6, 3, 2, 1, 0 are reserved and should be set to "0"
XTAL load cap = 3.5pF+ (0.125 x XTALCAP[7:0]) , 3.5pF to 35.4pF; Each XTAL pin to GND;
(For example, "00000001"=0.125pF, "00000010"=0.25pF, "00000100"=0.5pF); Default = "00000000";
PLL0 LOOP FILTER SETTING
P LL0 MULTIPLIER SETTING
CONFIG0 will be sele cted if GINx are disabled and operating in MFC mode.
N0[11:0]_CONFIGx - Part of PLL0 M Integer Feedback Divider Values (see equation below) - For 4 Configurations (Default value is '0');
A 0[3:0]_CONFIGx - Part of PLL0 M Integer Feedback Divider Values (see equation below) - For 4 Configurations (Default value is '0');
S SC_OFFSET0[5:0] - Spread Spectrum Fractional Multiplier Offset Value. S ee Spread Spectrum S ettings in register address range
0x60-0x67
Total Multiplier Value M0 = 2 * N0[11:0] + A0 + 1 + SS_OFFSET0 * 1/64
When A0[3:0] = 0 and spread spectrum disabled, M0= 2 * N0[11:0];
When A0[3:0] > 0 and spread spectrum disabled, M0 = 2 * N0[11:0] + A0 + 1;
(Note : A < N-1, i.e. valid M values are 2, 4, 6, 8, 9, 10, 11, 12, 13, ..., 4095 assuming within fPFD and fVCO spec);
S P=Shutdown/OE Polarity for SHUTDOWN/OE signal pin, ("0"= Active High (Default), "1"= Active Low);
OE x=Output Di sable Functi on for OUTx, ("1"=OUTx disabled base d on OE pin (De fault for OUT2 -6, Disable mode is defined by OEMx
bits), "0"= Outputs enabled and no association with OE pin (Default));
OS x=Output Power Suspend function for OUTx, ("1"=OUTx will be suspended on GIN3/SUSPEND pin (MFC="1"), "0"= Always Enabled
(Defa ult));
P LLSx=Determines which PLLx to suspend when GIN3 is programmed to be used as SUS PEND, It suspends all the outputs associated
with that PLL, ("1"= suspends based on SUSPEND pin, "0"= PLL enabled and no association with SUSP END pin (Default)); It over-rides
OS x bits;
S H=Determines the function of the SHUTDOWN/OE signal pin. ("1"=Global Shutdown; this over-ri des OEx and OSx bits, "0"=Ouput
E nable/Disable (Default))
OK C=clock OK count, "0"=8 cycles, "1"=1024 cycles (Default) of Input Clocks for Revertive Switchover Mode:
A ddress 0x1D, Bit 7; Address 0x1E, Bits [7:3] are reserved and should be set to "0"
INDUSTRIAL TEMPERATURE RANGE
No registers exist.
No registers exist
DES CRIPTION