IDT5V9885CPFI IDT, Integrated Device Technology Inc, IDT5V9885CPFI Datasheet - Page 15

• Manufacturer Part Number: IDT5V9885CPFI
• Description: IC CLK GEN 3.3V EEPROM 32-TQFP
• Manufacturer: IDT, Integrated Device Technology Inc
• Type: Clock Generatorr

Specifications of IDT5V9885CPFI

• Pll: Yes with Bypass
• Input: LVCMOS, LVTTL, Crystal
• Output: LVCMOS, LVDS, LVPECL, LVTTL
• Number Of Circuits: 1
• Ratio - Input:output: 2:8
• Differential - Input:output: No/Yes
• Frequency - Max: 500MHz
• Divider/multiplier: Yes/Yes
• Voltage - Supply: 3.135 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 32-TQFP, 32-VQFP
• Frequency-max: 500MHz
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 5V9885CPFI

MODE2 - Manual Frequency Control (MFC=0) Mode for all PLLs
Dx, Mx, RZx, CZx, CPx, and IPx configurations for each PLL. GIN0 and GIN1 become configuration selection pins for D0 and M0 of PLL0, GIN2 and GIN3
become configuration selection pins for PLL1, and GIN4 and GIN5 become configuration selection pins for D2 and M2 of PLL2. The output GOUT0 will become
an indicator for loss of PLL lock (LOSS_LOCK). GOUT1 pin will become an indicator for loss of the primary clock (LOSS_CLKIN).
set of PM bits (See the PRE-SCALERS, FEEDBACK-DIVIDERS, POST-DIVIDERS section for more detail on the PM bits). Use the ODIV bit to choose which
post-divider configuration to associate with a specific PLL configuration. For example, if ODIV2_CONFIG2=1, then when Config2 is selected Qx[9:0]_CONFIG1
is selected as the post-divider value to be used. Note that there is an ODIVx bit for each of the PLL configurations. In this way, the post-divider values can change
with the configuration.
MODE3 - I
will become an indicator for loss of PLL lock (LOSS_LOCK). GOUT1 pin will become an indicator for loss of the primary clock (LOSS_CLKIN). GIN2 and GIN4
are not available to users.
MODE4 - JTAG Programming Mode
(JTAG reset) and CLK_SEL signal pins, respectively. The output GOUT0 will become JTAG TDO signal, and GOUT1 will be an indicator for loss of the selected
clock (LOSS_CLKIN).
NOTE:
1.
IDT5V9885C
3.3V EEPROM PROGRAMMABLE CLOCK GENERATOR
GIN1 Pin
GIN3 Pin
In this mode, the configuration of PLL0, PLL1, and PLL2 can be changed during operation. The GINx pins are used to control the selection of up to four different
The output banks will have two different P configurations to choose from for each of the four PLL configurations. Each of the two P configurations has its own
To enter this mode, users must set MFC bit to "0", and I
In this mode, GIN0, GIN1, GIN3 and GIN5 become SDAT (I
To enter this mode, I
In this mode, GIN0, GIN1, GIN2, GIN3, GIN4 and GIN5 will become TDI (JTAG data in), TCK (JTAG clock), TMS (JTAG control signal), SUSPEND, TRST
To enter this mode, I
The PLL(s) will lock onto the primary clock and the manual switchover can be controlled by the PRIMCLK bit.
Multi-Purpose pins
0
0
1
1
0
0
1
1
GOUT0
GOUT1
2
GIN0
GIN1
GIN2
GIN3
GIN4
GIN5
C Programming Mode
GIN0 Pin
GIN2 Pin
0
1
0
1
0
1
0
1
2
2
C/JTAG pin must be set LOW.
C/JTAG pin must be set HIGH.
PLL0 Configuration Selection (Mode 2)
PLL1 Configuration Selection (Mode 2)
LOSS_CLKIN
LOSS_LOCK
Configuration 0
Configuration 1
Configuration 2
Configuration 3
Configuration 0
Configuration 1
Configuration 2
Configuration 3
SUSPEND
CLK_SEL
Mode1
GIN0
GIN1
GIN2
n/a
2
C/JTAG pin must be left floating.
2
C data), SCLK (I
LOSS_CLKIN
LOSS_LOCK
15
2
C clock), SUSPEND and CLK_SEL signal pins, respectively. The output GOUT0
GIN5
Mode2
GIN0
GIN1
GIN2
GIN3
GIN4
Manual Frequency Control modes
GIN5 Pin
(1)
0
0
1
1
GIN4 Pin
0
1
0
1
LOSS_CLKIN
SUSPEND
CLK_SEL
JTAG
TRST
PLL2 Configuration Selection (Mode 2)
TMS
TCK
TDO
TDI
INDUSTRIAL TEMPERATURE RANGE
Configuration 0
Configuration 1
Configuration 2
Configuration 3
LOSS_CLKIN
LOSS_LOCK
SUSPEND
CLK_SEL
SCLK
SDAT
I
n/a
n/a
2
C