IDT5V9885CPFI IDT, Integrated Device Technology Inc, IDT5V9885CPFI Datasheet - Page 21

• Manufacturer Part Number: IDT5V9885CPFI
• Description: IC CLK GEN 3.3V EEPROM 32-TQFP
• Manufacturer: IDT, Integrated Device Technology Inc
• Type: Clock Generatorr

Specifications of IDT5V9885CPFI

• Pll: Yes with Bypass
• Input: LVCMOS, LVTTL, Crystal
• Output: LVCMOS, LVDS, LVPECL, LVTTL
• Number Of Circuits: 1
• Ratio - Input:output: 2:8
• Differential - Input:output: No/Yes
• Frequency - Max: 500MHz
• Divider/multiplier: Yes/Yes
• Voltage - Supply: 3.135 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 32-TQFP, 32-VQFP
• Frequency-max: 500MHz
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 5V9885CPFI

be asserted. After a stable and valid primary clock source is present, the input clock selection will automatically switch back to the primary clock source and
LOSS_CLKIN signal will be deasserted. The CLK_SEL pin can be left floating in this auto-revertive mode. Note that both clock inputs must be at the same
frequency (within1000 ppm) in order for the auto-revertive switchover to function properly. If both reference clocks are at different frequencies, the device
will always remain on the primary clock unless it is absent for two secondary clock cycles.
CLOCK SWITCH MATRIX AND OUTPUTS
and clock source is routed to which output bank via the SRCx bits (0x34, 0x35). Each output bank has its own set of SRC bits. Refer to the RAM table for
more information. Note that OUT1 will be based off the reference clock and the only output bank toggling under the default RAM bit settings.
by the LVLx bits (0x54, 0x58). Each output bank has individual slew-rate control (SLEWx bits). Each output can be individually inverted (INVx bits);
when using LVPECL or LVDS modes, one of the outputs in each LVPECL/LVDS pair should be inverted. All output banks except OUT1 have a
programmable 10-bit post-divider (Qx bits) with two selectable divide configurations via the ODIVx bits.
differential outputs are not slew rate programmable in LVPECL or LVDS modes. SLEW4 and/or SLEW5 must be set to 2.75V/ns for stable output operation
. For LVTTL output frequency rates higher than 100MHz, a slew rate of 2V/ns or greater should be selected. The post-dividers can be disabled using
the PMx bit, which is described in the PRE-SCALER, FEEDBACK-DIVIDER, AND POST-DIVIDER section. Each output can also be enabled/disabled,
which is described in the 'SHUTDOWN/SUSPEND/ENABLE of OUTPUTS' section. Refer to the RAM table for all binary settings.
HIGH LEVEL BLOCK DIAGRAM FOR CONFIGURATION SCHEME
NOTE: Diagram does not represent actual number of die on chip.
IDT5V9885C
3.3V EEPROM PROGRAMMABLE CLOCK GENERATOR
Revertive
The input clock selection will switch to the secondary clock source when there are no transitions on the primary clock source. LOSS_CLKIN signals will
All three PLL outputs and the currently selected input clock source are routed into and through a clock matrix. The user is able to select which PLL output
Outputs 1, 2 and 3 are 3.3V LVTTL. Outputs banks 4 and 5 can be 3.3V LVTTL, LVPECL or LVDS. The LVDS and LVPECL selection is determined
There are four settings for the programmable slew rate, 0.7V/ns, 1.25V/ns, 2V/ns, and 2.75V/ns; this only applies to the 3.3V LVTTL outputs. The
I C or JTAG
2
interface
I/Os
PLLs and Control
Interface Block
Programming
Blocks
Configuration
Volatile
21
Configuration
Non-Volatile
EEPROM
Cell
INDUSTRIAL TEMPERATURE RANGE
I/Os
Write Enable