IDT5V9885CPFI IDT, Integrated Device Technology Inc, IDT5V9885CPFI Datasheet - Page 14

• Manufacturer Part Number: IDT5V9885CPFI
• Description: IC CLK GEN 3.3V EEPROM 32-TQFP
• Manufacturer: IDT, Integrated Device Technology Inc
• Type: Clock Generatorr

Specifications of IDT5V9885CPFI

• Pll: Yes with Bypass
• Input: LVCMOS, LVTTL, Crystal
• Output: LVCMOS, LVDS, LVPECL, LVTTL
• Number Of Circuits: 1
• Ratio - Input:output: 2:8
• Differential - Input:output: No/Yes
• Frequency - Max: 500MHz
• Divider/multiplier: Yes/Yes
• Voltage - Supply: 3.135 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 32-TQFP, 32-VQFP
• Frequency-max: 500MHz
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 5V9885CPFI

CONFIGURING THE MULTI-PURPOSE I/Os
(GIN0, GIN1, GIN2, GIN3, GIN4, GIN5) have different uses depending on the mode of operation. The four available modes of operation are:
The post-divider should never be disabled in any of the two P configurations unless the output bank will never be used during normal operation. The PLL's
loop filter settings also has four different configurations to store and select from. This will be explained in the MODE1 and MODE2 sections. The use of the GINx
pins in MFC mode control the selection of these configurations.
In this mode, only 8 configurations of PLL0 can be changed during operation. The GIN0, GIN1 and GIN2 pins control the selection of eight different
configurations (D, M, Rz, Cz, Cp and Ip) of PLL0. GIN3 becomes PLL SUSPEND pin, GIN4 is not available to users, and GIN5 becomes CLK_SEL pin.
The output GOUT0 will become an indicator for loss of PLL lock (LOSS_LOCK). GOUT1 pin will become an indicator for loss of the primary clock
(LOSS_CLKIN).
The PLL0 has 4 sets of dedicated registers for D, M, Rz, Cz, Cp, Ip and ODIV. For additional 4 sets of registers, the PLL0 uses registers from CONFIG2
and CONFIG3 of PLL1 and PLL2. The
configuration will be set to CONFIG0 of PLL1 and CONFIG0 of PLL2. (Please see page 18 for register location.)
The output banks will each have two P configurations that can be associated with each of the PLL configurations. Each of the two P configurations has its
own set of PM bits (See the PRE-SCALERS, FEEDBACK-DIVIDERS, POST-DIVIDERS section for more detail on the PM bits). Use the ODIV bit to
choose which post-divider configuration to associate with a specific PLL configuration.
To enter this mode, users must set MFC bit to “1”, and I2C/JTAG pin must be left floating.
NOTE:
1. Please see detail description in Loss of Lock and Input Clock section.
IDT5V9885C
3.3V EEPROM PROGRAMMABLE CLOCK GENERATOR
The 5V9885C can operate in four distinct modes. These modes are controlled by the MFC bit (0x04) and the I
1)
2)
3)
4)
Along with the GINx pins are also GOUTx output pins that can take up a different function depending on the mode of operation. See table below for description.
Each PLL's programming registers can store up to four different Dx and Mx configurations in combination with two different P configurations in MFC modes.
MODE1 - Manual Frequency Control (MFC=1) Mode for PLL0 Only
Multi-Purpose Pins
GIN2 Pin
Manual Frequency Control (MFC) Mode for PLL0 Only
Manual Frequency Control (MFC) Mode for all three PLLs
I
JTAG Programming Mode
2
C Programming Mode
GOUT0
GOUT1
0
0
0
0
1
1
1
1
GIN0
GIN1
GIN2
GIN3
GIN4
GIN5
GIN1 Pin
Other Signal Functions
TDO / LOSS_LOCK
0
0
1
1
0
0
1
1
LOSS_CLKIN
PLL1 and PLL2 will still be fully operational, but have only one fixed configuration in this mode, and the default
SCLK / TCK
SDAT / TDI
SUSPEND
CLK_SEL
TRST
TMS
GIN0 Pin
0
1
0
1
0
1
0
1
I
I
JTAG control signal to the TAP controller state machine
Suspends all outputs of PLL (Active High)
JTAG active LOW input to asynchronously reset the BST
Reference clock select between XTALIN/REFIN and CLKIN
Detects loss of the primary clock source
JTAG serial data output / Detects loss of PLL lock
2
2
C serial data input / JTAG serial data input
C clock input / JTAG clock input
14
PLL0 Configuration Selection (Mode 1)
Signal Description
Configuration 0
Configuration 1
Configuration 2
Configuration 3
Configuration 4
Configuration 5
Configuration 6
Configuration 7
(1)
2
INDUSTRIAL TEMPERATURE RANGE
C/JTAG pin. The general purpose I/O pins
(1)