IDT5V9885CPFI IDT, Integrated Device Technology Inc, IDT5V9885CPFI Datasheet - Page 26

• Manufacturer Part Number: IDT5V9885CPFI
• Description: IC CLK GEN 3.3V EEPROM 32-TQFP
• Manufacturer: IDT, Integrated Device Technology Inc
• Type: Clock Generatorr

Specifications of IDT5V9885CPFI

• Pll: Yes with Bypass
• Input: LVCMOS, LVTTL, Crystal
• Output: LVCMOS, LVDS, LVPECL, LVTTL
• Number Of Circuits: 1
• Ratio - Input:output: 2:8
• Differential - Input:output: No/Yes
• Frequency - Max: 500MHz
• Divider/multiplier: Yes/Yes
• Voltage - Supply: 3.135 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 32-TQFP, 32-VQFP
• Frequency-max: 500MHz
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 5V9885CPFI

I
I
NOTE:
1. A device must internally provide a hold time of at least 300ns for the SDAT signal (referred to the V
of SCLK.
I
NOTE:
1. A device must internally provide a hold time of at least 300ns for the SDAT signal (referred to the V
of SCLK.
IDT5V9885C
3.3V EEPROM PROGRAMMABLE CLOCK GENERATOR
2
2
2
t
t
Symbol
Symbol
t
Symbol
t
t
t
t
t
SU
HD
t
SU
HD
t
C BUS DC CHARACTERISTICS
C BUS AC CHARACTERISTICS FOR STANDARD MODE
C BUS AC CHARACTERISTICS FOR FAST MODE
SU
HD
SU
SU
HD
SU
F
F
V
t
t
V
t
t
t
t
t
t
V
V
HIGH
HIGH
SCLK
:
:
OVD
C
LOW
SCLK
:
:
OVD
C
LOW
I
BUF
BUF
:
:
:
:
:
:
HYS
START
START
t
START
START
t
t
t
IN
DATA
DATA
R
STOP
DATA
DATA
R
STOP
OL
F
F
IH
IL
B
B
Parameter
Input HIGH Level
Input LOW Level
Hysteresis of Inputs
Input Leakage Current
Output LOW Voltage
Parameter
Serial Clock Frequency (SCLK)
Bus free time between STOP and START
Setup Time, START
Hold Time, START
Setup Time, data input (SDAT)
Hold Time, data input (SDAT)
Output data valid from clock
Capacitive Load for Each Bus Line
Rise Time, data and clock (SDAT, SCLK)
Fall Time, data and clock (SDAT, SCLK)
HIGH Time, clock (SCLK)
LOW Time, clock (SCLK)
Setup Time, STOP
Parameter
Serial Clock Frequency (SCLK)
Bus free time between STOP and START
Setup Time, START
Hold Time, START
Setup Time, data input (SDAT)
Hold Time, data input (SDAT)
Output data valid from clock
Capacitive Load for Each Bus Line
Rise Time, data and clock (SDAT, SCLK)
Fall Time, data and clock (SDAT, SCLK)
HIGH Time, clock (SCLK)
LOW Time, clock (SCLK)
Setup Time, STOP
(1)
(1)
Conditions
I
OL
= 3 mA
26
IHMIN
IHMIN
20 + 0.1 * C
20 + 0.1 * C
0.05 * V
0.7 * V
of the SCLK signal) to bridge the undefined region of the falling edge
of the SCLK signal) to bridge the undefined region of the falling edge
Min
Min
Min
250
100
4.7
4.7
4.7
1.3
0.6
0.6
0.6
1.3
0.6
0
4
0
4
4
0
0
DD
DD
B
B
INDUSTRIAL TEMPERATURE RANGE
Typ
Typ
Typ
0.3 * V
±1.0
1000
Max
Max
Max
3.45
100
400
300
400
400
300
300
0.4
0.9
DD
Unit
Unit
KHz
Unit
KHz
µA
µs
µs
µs
µs
µs
pF
µs
µs
µs
µs
µs
µs
µs
µs
pF
µs
µs
µs
ns
ns
ns
ns
ns
ns
V
V
V
V