X1228S14IZ Intersil, X1228S14IZ Datasheet
X1228S14IZ
Specifications of X1228S14IZ
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X1228S14IZ Summary of contents
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... Low Voltage Timer Reset CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. | 1-888-INTERSIL or 1-888-468-3774 Intersil (and design registered trademark of Intersil Americas Inc. All other trademarks mentioned are the property of their respective owners. X1228 ™ 4K (512 x 8), 2-Wire RTC FN8100 ...
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... X1228V ZAN X1228V14I-2.7A X1228V AP X1228V14IZ-2.7A (Note) X1228V ZAP X1228S14-2.7* X1228S F X1228S14Z-2.7* (Note) X1228S ZF X1228S14I-2.7 X1228S G X1228S14IZ-2.7 (Note) X1228S ZG X1228V14-2.7 X1228V F X1228V14Z-2.7 (Note) X1228V ZF X1228V14I-2.7 X1228V G X1228V14IZ-2.7 (Note) X1228V ZG *Add "T1" suffix for tape and reel. Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations ...
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PIN DESCRIPTIONS PIN ASSIGNMENTS Pin Number SOIC/TSSOP Symbol 1 X1 X1. The X1 pin is the input of an inverting amplifier. An external 32.768kHz quartz crystal is used with the X1228 to supply a timebase for the real time clock. ...
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ABSOLUTE MAXIMUM RATINGS Temperature Under Bias ................... -65°C to +135°C Storage Temperature ........................ -65°C to +150°C Voltage and PHZ/IRQ CC BACK pin (respect to ground) ............................-0.5V to 7.0V Voltage on SCL, SDA, X1 and X2 pin ...
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Notes: (1) The device enters the Active state after any start, and remains active: for 9 clock cycles if the Device Select Bits in the Slave Address Byte are incorrect or until 200nS after a stop ending a read or ...
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AC Specifications (T = -40°C to +85°C, VCC = +2.7V to +5.5V, unless otherwise specified.) A Symbol f SCL Clock Frequency SCL t Pulse width Suppression Time at inputs IN t SCL LOW to SDA Data Out Valid AA t ...
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Write Cycle Timing SCL 8th Bit of Last Byte SDA Power-up Timing Symbol (1) t Time from Power-up to Read PUR (1) t Time from Power-up to Write PUW Notes: (1) Delays are measured from the time V V slew ...
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V Programming Timing Diagram TRIP TRIP RESET VPS SCL SDA AEh V Programming Parameters TRIP Parameter t V Program Enable Voltage Setup time VPS TRIP ...
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DESCRIPTION The X1228 device is a Real Time Clock with clock/calendar, two polled alarms with integrated 512x8 EEPROM, oscillator compensation, CPU Supervisor (POR/LVS and WDT) and battery backup switch. The oscillator uses an external, low-cost 32.768kHz crystal. All compensation and ...
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... For example, a >20ppm frequency deviation translates into an accuracy of >1 minute per month. These parameters are available from the crystal manufacturer. Intersil’s RTC family provides on-chip crystal compensation networks to adjust load- capacitance to tune oscillator frequency from +116 ppm to -37 ppm when using a 12.5 pF load crystal. For more detail information see the Application section ...
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CLOCK/CONTROL REGISTERS (CCR) The Control/Clock Registers are located in an area separate from the EEPROM array and are only accessible following a slave byte of “1101111x” and reads or writes to addresses [0000h:003Fh]. The clock/control memory map has memory addresses ...
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Table 1. Clock/Control Memory Map Reg Addr. Type Name 7 000F Alarm1 Y2K1 0 (EEPROM) 000E DWA1 EDW1 000D YRA1 000C MOA1 EMO1 000B DTA1 EDT1 000A HRA1 EHR1 0009 MNA1 EMN1 0008 SCA1 ESC1 0007 Alarm0 Y2K0 0 (EEPROM) ...
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STATUS REGISTER (SR) The Status Register is located in the CCR memory map area at address 003Fh. This is a volatile register only and is used to control the WEL and RWEL write enable latches, read two power status and ...
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Table 4. Watchdog Timer Time-Out Options Watchdog Time-Out Period WD1 WD0 0 0 1.75 seconds 0 1 750 milliseconds 1 0 250 milliseconds 1 1 Disabled (default) INTERRUPT CONTROL AND FREQUENCY OUTPUT REGISTER (INT) Interrupt Control and Status Bits (IM, ...
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... The values calculated above are typical, and total load capacitance seen by the crystal will include approxi- mately 2pF of package and board capacitance in addi- tion to the ATR value. See Application section and Intersil’s Application Note AN154 for more information. WRITING TO THE CLOCK/CONTROL REGISTERS Changing ...
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LOW VOLTAGE RESET OPERATION When a power failure occurs, and the voltage to the part drops below a fixed v voltage, a reset pulse is TRIP issued to the host microcontroller. The circuitry moni- tors the V line with a ...
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Figure 5. Set V Level Sequence (V TRIP RESET SCL SDA AEh Note: BP0, BP1, BP2 must be disabled. Resetting the V Voltage TRIP This procedure is used to set ...
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SERIAL COMMUNICATION Interface Conventions The device supports a bidirectional bus oriented proto- col. The protocol defines any device that sends data onto the bus as a transmitter, and the receiving device as the receiver. The device controlling the transfer is ...
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Figure 8. Valid Start and Stop Conditions SCL SDA Figure 9. Acknowledge Response From Receiver SCL from Master Data Output from Transmitter Data Output from Receiver Start DEVICE ADDRESSING Following a start condition, the master must output a Slave Address ...
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Figure 10. Slave Address, Word Address, and Data Bytes (64 Byte pages) Device Identifier Array CCR Write Operations Byte Write For a write operation, the device requires the Slave Address ...
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A write to a protected block of memory is ignored, but will still receive an acknowledge. At the end of the write command, the X1228 will not initiate an internal write cycle, and will continue to ACK commands. Page Write ...
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Acknowledge Polling Disabling of the inputs during nonvolatile write cycles can be used to take advantage of the typical 5mS write cycle time. Once the stop condition is issued to indi- cate the end of the master’s byte load operation, ...
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Random Read Random read operations allows the master to access any location in the X1228. Prior to issuing the Slave Address Byte with the R/W bit set to zero, the master must first perform a “dummy” write operation. The master ...
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... In addition to the analog compensation afforded by the adjustable load capacitance, a digital compensation feature is available for the Intersil RTC family. There are three bits known as the Digital Trimming Register or DTR, and they operate by adding or skipping pulses in the clock signal. The range provided is ±30ppm in increments of 10ppm ...
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... RTC. Care needs to be taken in layout of the RTC circuit to avoid noise pickup. Below in Fig- ure suggested layout for the X1228 device. Figure 15. Suggested Layout for Intersil RTC in SO-14 R1 10k U1 XTAL1 X1228 32 ...
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... Many types of batteries can be used with the Intersil RTC products. 3.0V or 3.6V Lithium batteries are appropriate, and sizes are available that can power a Intersil RTC device for years. Another option is to use a supercapacitor for applications where Vcc may disappear intermittently for short periods of time. ...
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Referring to Figure 16, Vtrip applies to the “Internal Vcc” node which powers the entire device. This means that if Vcc is powered down and the battery voltage at Vback is higher than the Vtrip voltage, then the entire chip ...
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Small Outline Package Family (SO PIN #1 I.D. MARK 0.010 SEATING PLANE 0.004 C 0.010 MDP0027 SMALL OUTLINE PACKAGE FAMILY (SO) SYMBOL SO-8 SO-14 ...
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... Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use ...