X1228S14IZ Intersil, X1228S14IZ Datasheet - Page 22

• Manufacturer Part Number: X1228S14IZ
• Description: IC RTC/CAL/SUP/ALRM 4K EE 14SOIC
• Manufacturer: Intersil
• Type: Clock/Calendar/EEPROMr

Specifications of X1228S14IZ

• Memory Size: 4K (512 x 8)
• Time Format: HH:MM:SS (12/24 hr)
• Date Format: YY-MM-DD-dd
• Interface: I²C, 2-Wire Serial
• Voltage - Supply: 2.7 V ~ 5.5 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 14-SOIC (3.9mm Width), 14-SOL
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Acknowledge Polling
Disabling of the inputs during nonvolatile write cycles
can be used to take advantage of the typical 5mS write
cycle time. Once the stop condition is issued to indi-
cate the end of the master’s byte load operation, the
X1228 initiates the internal nonvolatile write cycle.
Acknowledge polling can begin immediately. To do
this, the master issues a start condition followed by the
Memory Array Slave Address Byte for a write or read
operation (AEh or AFh). If the X1228 is still busy with
the nonvolatile write cycle then no ACK will be
returned. When the X1228 has completed the write
operation, an ACK is returned and the host can pro-
ceed with the read or write operation. Refer to the flow
chart in Figure 15. Note: Do not use the CCR Salve
byte (DEh or DFh) for Acknowledge Polling.
Read Operations
There are three basic read operations: Current
Address Read, Random Read, and Sequential Read.
Current Address Read
Internally the X1228 contains an address counter that
maintains the address of the last word read incre-
mented by one. Therefore, if the last read was to
address n, the next read operation would access data
from address n+1. On power-up, the sixteen bit
address is initialized to 0h. In this way, a current
address read immediately after the power-on reset
can download the entire contents of memory starting
at the first location.Upon receipt of the Slave Address
Byte with the R/W bit set to one, the X1228 issues an
acknowledge, then transmits eight data bits. The mas-
ter terminates the read operation by not responding
with an acknowledge during the ninth clock and issu-
ing a stop condition. Refer to Figure 14 for the
address, acknowledge, and data transfer sequence.
Figure 14. Current Address Read Sequence
22
Signals from
the Master
SDA Bus
Signals from
the Slave
S
a
t
r
t
1
Address
Slave
X1228
1
1
1
1
Figure 15. Acknowledge Polling Sequence
It should be noted that the ninth clock cycle of the read
operation is not a “don’t care.” To terminate a read
operation, the master must either issue a stop condi-
tion during the ninth cycle or hold SDA HIGH during
the ninth clock cycle and then issue a stop condition.
A
C
K
Issue Memory Array Slave
AFh (Read) or AEh (Write)
Data
Cycle complete. Continue
command sequence?
Byte load completed
Enter ACK Polling
by issuing STOP.
Continue normal
nonvolatile write
Read or Write
Address Byte
Issue START
PROCEED
command
returned?
sequence
ACK
S
o
p
t
YES
YES
NO
NO
Issue STOP
Issue STOP
May 18, 2006
FN8100.4