ADC0804LCN Intersil, ADC0804LCN Datasheet - Page 4

• Manufacturer Part Number: ADC0804LCN
• Description: IC ADC 8-BIT 10KSPS 1LSB 20-DIP
• Manufacturer: Intersil

Specifications of ADC0804LCN

• Number Of Bits: 8
• Sampling Rate (per Second): 10k
• Data Interface: Parallel
• Number Of Converters: 1
• Voltage Supply Source: Single Supply
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Through Hole
• Package / Case: 20-DIP (0.300", 7.62mm)
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: ADC0804LCNIN; ADC0804LCNIN

Timing Waveforms
Electrical Specifications
NOTES:
DC DIGITAL LEVELS AND DC SPECIFICATIONS V+ = 5V, and T
CONTROL INPUTS (Note 7)
Logic “1“ Input Voltage (Except Pin 4 CLK
IN), V
Logic “0“ Input Voltage (Except Pin 4 CLK
IN), V
CLK IN (Pin 4) Positive Going Threshold
Voltage, V+
CLK IN (Pin 4) Negative Going Threshold
Voltage, V-
CLK IN (Pin 4) Hysteresis, V
Logic “1” Input Current (All Inputs), I
Logic “0” Input Current (All Inputs), I
Supply Current (Includes Ladder Current), I+ f
DATA OUTPUTS AND INTR
Logic “0” Output Voltage, V
Logic “1” Output Voltage, V
Three-State Disabled Output Leakage (All
Data Buffers)
Output Short Circuit Current, I
Output Short Circuit Current, I
2. All voltages are measured with respect to GND, unless otherwise specified. The separate AGND point should always be wired to the DGND,
3. For V
4. With V+ = 6V, the digital logic interfaces are no longer TTL compatible.
5. With an asynchronous start pulse, up to 8 clock periods may be required before the internal clock phases are proper to start the conversion process.
6. The CS input is assumed to bracket the WR strobe input so that timing is dependent on the WR pulse width. An arbitrarily wide pulse width will
7. CLK IN (pin 4) is the input of a Schmitt trigger circuit and is therefore specified separately.
8. None of these A/Ds requires a zero-adjust. However, if an all zero code is desired for an analog input other than 0V, or if a narrow full scale span exists
being careful to avoid ground loops.
forward conduct for analog input voltages one diode drop below ground or one diode drop greater than the V+ supply. Be careful, during testing
at low V+ levels (4.5V), as high level analog inputs (5V) can cause this input diode to conduct - especially at elevated temperatures, and cause
errors for analog inputs near full scale. As long as the analog V
be correct. To achieve an absolute 0V to 5V input voltage range will therefore require a minimum supply voltage of 4.950V over temperature
variations, initial tolerance and loading.
hold the converter in a reset mode and the start of conversion is initiated by the low to high transition of the WR pulse (see Timing Diagrams).
(for example: 0.5V to 4V full scale) the V
INH
INL
IN(-)
CLK
CLK
RD
CS
, I
PARAMETER
LO
V
IN(+)
the digital output code will be 0000 0000. Two on-chip diodes are tied to each analog input (see Block Diagram) which will
V+
FIGURE 1A. t
OL
OH
H
SOURCE
SINK
4
(Notes 2, 8) (Continued)
C
INHI
INLO
L
1H
10K
IN(-)
V+ = 5.25V
V+ = 4.75V
V
V
l
l
V
V
V
V
O
O
DATA
OUTPUT
CLK
lN
lN
OUT
OUT
OUT
OUT
input can be adjusted to achieve this. See the Zero Error description in this data sheet.
= 1.6mA, V+ = 4.75V
= -360 A, V+ = 4.75V
= 5V
= 0V
= 640kHz, T
= 0V
= 5V
Short to GND, T
Short to V+, T
ADC0803, ADC0804
TEST CONDITIONS
A
= 25
A
IN
= 25
A
MIN
o
does not exceed the supply voltage by more than 50mV, the output code will
= 25
C and CS = Hl
o
to T
C
o
C
MAX
, Unless Otherwise Specified
OUTPUTS
MIN
DATA
FIGURE 1B. t
2.0
2.7
1.5
0.6
2.4
4.5
9.0
-1
-3
-
-
-
-
-
RD
GND
2.4V
0.8V
V
OH
-0.005
0.005
TYP
3.1
1.8
1.3
1.3
16
6
-
-
-
-
-
-
1H
t
r
, C
= 20ns
t
r
10%
L
50%
= 10pF
90%
MAX
0.8
3.5
2.1
2.0
2.5
0.4
V+
90%
1
3
-
-
-
-
-
t
1H
UNITS
mA
mA
mA
V
V
V
V
V
V
V
A
A
A