IC DAC 8CH 114DB 192KHZ 48LQFP

CS4382A-CQZ

Manufacturer Part NumberCS4382A-CQZ
DescriptionIC DAC 8CH 114DB 192KHZ 48LQFP
ManufacturerCirrus Logic Inc
CS4382A-CQZ datasheets
 

Specifications of CS4382A-CQZ

Package / Case48-LQFPNumber Of Bits24
Data InterfaceSerialNumber Of Converters8
Voltage Supply SourceAnalog and DigitalPower Dissipation (max)680mW
Operating Temperature-40°C ~ 85°CMounting TypeSurface Mount
Conversion Rate192 KSPSResolution24 bit
Interface TypeSerialOperating Supply Voltage5 V
Operating Temperature Range+ 85 CMaximum Power Dissipation390 mW
Mounting StyleSMD/SMTNumber Of Dac Outputs8
Lead Free Status / RoHS StatusLead free / RoHS CompliantFor Use With598-1524 - BOARD EVAL FOR CS4382A DAC
Settling Time-Other names598-1061
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
Page 31
32
Page 32
33
Page 33
34
Page 34
35
Page 35
36
Page 36
37
Page 37
38
Page 38
39
Page 39
40
Page 40
41
42
43
44
45
46
47
48
49
50
Page 33/50

Download datasheet (982Kb)Embed
PrevNext
6. REGISTER DESCRIPTION
Note:
All registers are read/write in I²C Mode and write only in SPI, unless otherwise noted.
6.1
Mode Control 1 (Address 01h)
7
6
CPEN
FREEZE
MCLKDIV
0
0
6.1.1
Control Port Enable (CPEN)
Default = 0
0 - Disabled
1 - Enabled
Function:
This bit defaults to 0, allowing the device to power-up in Stand-Alone Mode. The Control Port Mode can
be accessed by setting this bit to 1. This will allow the operation of the device to be controlled by the reg-
isters and the pin definitions will conform to Control Port Mode. To accomplish a clean power-up, the user
should write this bit within 10 ms following the release of Reset.
6.1.2
Freeze Controls (FREEZE)
Default = 0
0 - Disabled
1 - Enabled
Function:
This function allows modifications to be made to the registers without the changes taking effect until the
FREEZE is disabled. To make multiple changes in the Control Port registers take effect simultaneously,
enable the FREEZE Bit, make all register changes, then Disable the FREEZE bit.
6.1.3
Master Clock Divide Enable (MCLKDIV)
Default = 0
0 - Disabled
1 - Enabled
Function:
The MCLKDIV bit enables a circuit which divides the externally applied MCLK signal by 2 prior to all other
internal circuitry.
6.1.4
DAC Pair Disable (DACx_DIS)
Default = 0
0 - DAC Pair x Enabled
1 - DAC Pair x Disabled
Function:
When the bit is set, the respective DAC channel pair (AOUTAx and AOUTBx) will remain in a reset state.
It is advised that changes to these bits be made while the power-down (PDN) bit is enabled to eliminate
the possibility of audible artifacts.
DS618F2
5
4
3
DAC4_DIS
DAC3_DIS
0
0
0
CS4382A
2
1
0
DAC2_DIS
DAC1_DIS
PDN
0
0
1
33