IC DAC 8CH 114DB 192KHZ 48LQFP

CS4382A-CQZ

Manufacturer Part NumberCS4382A-CQZ
DescriptionIC DAC 8CH 114DB 192KHZ 48LQFP
ManufacturerCirrus Logic Inc
CS4382A-CQZ datasheets
 

Specifications of CS4382A-CQZ

Package / Case48-LQFPNumber Of Bits24
Data InterfaceSerialNumber Of Converters8
Voltage Supply SourceAnalog and DigitalPower Dissipation (max)680mW
Operating Temperature-40°C ~ 85°CMounting TypeSurface Mount
Conversion Rate192 KSPSResolution24 bit
Interface TypeSerialOperating Supply Voltage5 V
Operating Temperature Range+ 85 CMaximum Power Dissipation390 mW
Mounting StyleSMD/SMTNumber Of Dac Outputs8
Lead Free Status / RoHS StatusLead free / RoHS CompliantFor Use With598-1524 - BOARD EVAL FOR CS4382A DAC
Settling Time-Other names598-1061
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4. APPLICATIONS
The CS4382A serially accepts two’s-complement formatted PCM data at standard audio sample rates including 48,
44.1, and 32 kHz in SSM, 96, 88.2, and 64 kHz in DSM, and 192, 176.4, and 128 kHz in QSM. Audio data is input
via the serial data input pins (SDINx). The Left/Right Clock (LRCK) determines which channel is currently being input
on SDINx, and the Serial Clock (SCLK) clocks audio data into the input data buffer.
The CS4382A can be configured in Hardware Mode by the M0, M1, M2, M3, and DSD_EN pins and in Software
Mode through I²C or SPI.
4.1
Master Clock
MCLK/LRCK must be an integer ratio as shown in
cy at which words for each channel are input to the device. The MCLK-to-LRCK frequency ratio is detected
automatically during the initialization sequence by counting the number of MCLK transitions during a single
LRCK period. Internal dividers are then set to generate the proper internal clocks.
standard audio sample rates and the required MCLK and LRCK frequencies. Please note there is no re-
quired phase relationship, but MCLK, LRCK, and SCLK must be synchronous.
Sample
Speed Mode
Rate
(sample-rate range)
(kHz)
MCLK Ratio
32
Single-Speed
(4 to 50 kHz)
44.1
48
MCLK Ratio
64
Double-Speed
(50 to 100 kHz)
88.2
96
MCLK Ratio
176.4
Quad-Speed
(100 to 200 kHz)
192
Note:
These modes are only available in Software Mode by setting the MCLKDIV bit = 1.
4.2
Mode Select
In Hardware Mode, operation is determined by the Mode Select pins. The states of these pins are continu-
ally scanned for any changes; however, the mode should only be changed while the device is in reset
(RST pin low) to ensure proper switching from one mode to another. These pins require connection to sup-
ply or ground as outlined in
Tables 2
-
4
show the decode of these pins.
In Software Mode, the operational mode and data format are set in the FM and DIF registers. See
Interface Format (DIF)” on page 34
DS618F2
Table
1. The LRCK frequency is equal to Fs, the frequen-
MCLK (MHz)
256x
384x
512x
8.1920
12.2880
16.3840
11.2896
16.9344
22.5792
12.2880
18.4320
24.5760
128x
192x
256x
8.1920
12.2880
16.3840
11.2896
16.9344
22.5792
12.2880
18.4320
24.5760
64x
96x
128x
11.2896
16.9344
22.5792
12.2880
18.4320
24.5760
Table 1. Common Clock Frequencies
Figure
6. VLC supplies M0, M1, and M2. VLS supplies M3 and DSD_EN.
and
“Functional Mode (FM)” on page
CS4382A
Table 1
illustrates several
Software
Mode Only
768x
1024x*
24.5760
32.7680
33.8688
45.1584
36.8640
49.1520
384x
512x*
24.5760
32.7680
33.8688
45.1584
36.8640
49.1520
192x
256x*
33.8688
45.1584
36.8640
49.1520
“Digital
40.
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