EPM7064SLI44-7N Altera, EPM7064SLI44-7N Datasheet - Page 18

IC MAX 7000 CPLD 64 44-PLCC

EPM7064SLI44-7N

Manufacturer Part Number
EPM7064SLI44-7N
Description
IC MAX 7000 CPLD 64 44-PLCC
Manufacturer
Altera
Series
MAX® 7000r
Datasheet

Specifications of EPM7064SLI44-7N

Programmable Type
In System Programmable
Delay Time Tpd(1) Max
7.5ns
Voltage Supply - Internal
4.5 V ~ 5.5 V
Number Of Logic Elements/blocks
4
Number Of Macrocells
64
Number Of Gates
1250
Number Of I /o
36
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
44-PLCC
Voltage
5V
Memory Type
EEPROM
Number Of Logic Elements/cells
4
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Features
-
Other names
544-2017
EPM7064SLI44-7N
MAX 7000 Programmable Logic Device Family Data Sheet
Programming Times
The time required to implement each of the six programming stages can
be broken into the following two elements:
By combining the pulse and shift times for each of the programming
stages, the program or verify time can be derived as a function of the TCK
frequency, the number of devices, and specific target device(s). Because
different ISP-capable devices have a different number of EEPROM cells,
both the total fixed and total variable times are unique for a single device.
Programming a Single MAX 7000S Device
The time required to program a single MAX 7000S device in-system can
be calculated from the following formula:
t PROG
where: t
The ISP times for a stand-alone verification of a single MAX 7000S device
can be calculated from the following formula:
t
VER
where: t
18
A pulse time to erase, program, or read the EEPROM cells.
A shifting time based on the test clock (TCK) frequency and the
number of TCK cycles to shift instructions, address, and data into the
device.
Cycle
PTCK
=
t PPULSE
+
------------------------------- -
f
TCK
= Programming time
PROG
t
= Sum of the fixed times to erase, program, and
PPULSE
verify the EEPROM cells
Cycle
= Number of TCK cycles to program a device
PTCK
f
= TCK frequency
TCK
Cycle
VTCK
=
t
+
--------------------------------
VPULSE
f
TCK
= Verify time
VER
t
= Sum of the fixed times to verify the EEPROM cells
VPULSE
Cycle
= Number of TCK cycles to verify a device
VTCK
Altera Corporation

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