IC MAX 7000 CPLD 64 44-PLCC

EPM7064SLI44-7N

Manufacturer Part NumberEPM7064SLI44-7N
DescriptionIC MAX 7000 CPLD 64 44-PLCC
ManufacturerAltera
SeriesMAX® 7000
EPM7064SLI44-7N datasheet
 

Specifications of EPM7064SLI44-7N

Programmable TypeIn System ProgrammableDelay Time Tpd(1) Max7.5ns
Voltage Supply - Internal4.5 V ~ 5.5 VNumber Of Logic Elements/blocks4
Number Of Macrocells64Number Of Gates1250
Number Of I /o36Operating Temperature-40°C ~ 85°C
Mounting TypeSurface MountPackage / Case44-PLCC
Voltage5VMemory TypeEEPROM
Number Of Logic Elements/cells4Lead Free Status / RoHS StatusLead free / RoHS Compliant
Features-Other names544-2017
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Notes to tables:
(1)
These values are specified under the recommended operating conditions shown in
information on switching waveforms.
(2)
This parameter applies to MAX 7000E devices only.
(3)
This minimum pulse width for preset and clear applies for both global clear and array controls. The t
must be added to this minimum width if the clear or reset signal incorporates the t
path.
(4)
This parameter is a guideline that is sample-tested only and is based on extensive device characterization. This
parameter applies for both global and array clocking.
(5)
These parameters are measured with a 16-bit loadable, enabled, up/down counter programmed into each LAB.
(6)
The f
values represent the highest frequency for pipelined data.
MAX
(7)
Operating conditions: V
CCIO
(8)
The t
parameter must be added to the t
LPA
running in the low-power mode.
Table 27. EPM7032S External Timing Parameters (Part 1 of 2)
Symbol
Parameter
t
Input to non-registered output
PD1
t
I/O input to non-registered
PD2
output
t
Global clock setup time
SU
t
Global clock hold time
H
t
Global clock setup time of fast
FSU
input
t
Global clock hold time of fast
FH
input
t
Global clock to output delay
CO1
t
Global clock high time
CH
t
Global clock low time
CL
t
Array clock setup time
ASU
t
Array clock hold time
AH
t
Array clock to output delay
ACO1
t
Array clock high time
ACH
t
Array clock low time
ACL
t
Minimum pulse width for clear
CPPW
and preset
t
Output data hold time after
ODH
clock
t
Minimum global clock period
CNT
f
Maximum internal global clock
CNT
frequency
t
Minimum array clock period
ACNT
Altera Corporation
MAX 7000 Programmable Logic Device Family Data Sheet
= 3.3 V ± 10% for commercial and industrial use.
, t
, t
, t
, t
LAD
LAC
IC
EN
SEXP
Tables 27
and
28
show the EPM7032S AC operating conditions.
Conditions
-5
Min Max Min Max Min Max Min Max
C1 = 35 pF
5.0
C1 = 35 pF
5.0
2.9
0.0
2.5
0.0
C1 = 35 pF
3.2
2.0
2.0
0.7
1.8
C1 = 35 pF
5.4
2.5
2.5
(2)
2.5
C1 = 35 pF
(3)
1.0
5.7
(4)
175.4
5.7
Table
14. See
Figure 13
parameter into the signal
LAD
, t
, and t
parameters for macrocells
ACL
CPPW
Note (1)
Speed Grade
-6
-7
-10
6.0
7.5
6.0
7.5
4.0
5.0
7.0
0.0
0.0
0.0
2.5
2.5
3.0
0.0
0.0
0.5
3.5
4.3
2.5
3.0
4.0
2.5
3.0
4.0
0.9
1.1
2.0
2.1
2.7
3.0
6.6
8.2
2.5
3.0
4.0
2.5
3.0
4.0
2.5
3.0
4.0
1.0
1.0
1.0
7.0
8.6
142.9
116.3
100.0
7.0
8.6
for more
parameter
LPA
Unit
10.0
ns
10.0
ns
ns
ns
ns
ns
5.0
ns
ns
ns
ns
ns
10.0
ns
ns
ns
ns
ns
10.0
ns
MHz
10.0
ns
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