EPM7064SLI44-7N Altera, EPM7064SLI44-7N Datasheet - Page 8

IC MAX 7000 CPLD 64 44-PLCC

EPM7064SLI44-7N

Manufacturer Part Number
EPM7064SLI44-7N
Description
IC MAX 7000 CPLD 64 44-PLCC
Manufacturer
Altera
Series
MAX® 7000r
Datasheet

Specifications of EPM7064SLI44-7N

Programmable Type
In System Programmable
Delay Time Tpd(1) Max
7.5ns
Voltage Supply - Internal
4.5 V ~ 5.5 V
Number Of Logic Elements/blocks
4
Number Of Macrocells
64
Number Of Gates
1250
Number Of I /o
36
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
44-PLCC
Voltage
5V
Memory Type
EEPROM
Number Of Logic Elements/cells
4
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Features
-
Other names
544-2017
EPM7064SLI44-7N
MAX 7000 Programmable Logic Device Family Data Sheet
Figure 2. MAX 7000E & MAX 7000S Device Block Diagram
8
INPUT/OE2/GCLK2
INPUT/GCLRn
INPUT/GCLK1
6 to 16 I/O Pins
6 to 16 I/O Pins
INPUT/OE1
Control
Control
Block
Block
I/O
I/O
6
6
6 Output Enables
6 to16
6 to16
6 to16
6 to16
Figure 2
Logic Array Blocks
The MAX 7000 device architecture is based on the linking of high-
performance, flexible, logic array modules called logic array blocks
(LABs). LABs consist of 16-macrocell arrays, as shown in
Multiple LABs are linked together via the programmable interconnect
array (PIA), a global bus that is fed by all dedicated inputs, I/O pins, and
macrocells.
LAB A
LAB C
Macrocells
Macrocells
shows the architecture of MAX 7000E and MAX 7000S devices.
33 to 48
1 to 16
6 to16
6 to16
16
16
36
36
PIA
36
36
6 to16
6 to16
16
16
Macrocells
Macrocells
17 to 32
49 to 64
LAB D
LAB B
6 Output Enables
6 to16
6 to16
6 to16
6 to16
Control
Control
Block
Block
I/O
I/O
Altera Corporation
6
6
Figures 1
6 to 16 I/O Pins
6 to 16 I/O Pins
and 2.

Related parts for EPM7064SLI44-7N