EPM7064SLI44-7N Altera, EPM7064SLI44-7N Datasheet - Page 2

IC MAX 7000 CPLD 64 44-PLCC

EPM7064SLI44-7N

Manufacturer Part Number
EPM7064SLI44-7N
Description
IC MAX 7000 CPLD 64 44-PLCC
Manufacturer
Altera
Series
MAX® 7000r
Datasheet

Specifications of EPM7064SLI44-7N

Programmable Type
In System Programmable
Delay Time Tpd(1) Max
7.5ns
Voltage Supply - Internal
4.5 V ~ 5.5 V
Number Of Logic Elements/blocks
4
Number Of Macrocells
64
Number Of Gates
1250
Number Of I /o
36
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
44-PLCC
Voltage
5V
Memory Type
EEPROM
Number Of Logic Elements/cells
4
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Features
-
Other names
544-2017
EPM7064SLI44-7N
MAX 7000 Programmable Logic Device Family Data Sheet
Table 2. MAX 7000S Device Features
Feature
EPM7032S
Usable gates
600
Macrocells
32
Logic array
2
blocks
Maximum
36
user I/O pins
t
(ns)
5
PD
t
(ns)
2.9
SU
t
(ns)
2.5
FSU
t
(ns)
3.2
CO1
f
(MHz)
175.4
CNT
...and More
Features
2
EPM7064S
EPM7128S
1,250
2,500
64
128
4
8
68
100
5
6
2.9
3.4
2.5
2.5
3.2
4
175.4
147.1
Open-drain output option in MAX 7000S devices
Programmable macrocell flipflops with individual clear, preset,
clock, and clock enable controls
Programmable power-saving mode for a reduction of over 50% in
each macrocell
Configurable expander product-term distribution, allowing up to
32 product terms per macrocell
44 to 208 pins available in plastic J-lead chip carrier (PLCC), ceramic
pin-grid array (PGA), plastic quad flat pack (PQFP), power quad flat
pack (RQFP), and 1.0-mm thin quad flat pack (TQFP) packages
Programmable security bit for protection of proprietary designs
3.3-V or 5.0-V operation
TM
MultiVolt
I/O interface operation, allowing devices to
interface with 3.3-V or 5.0-V devices (MultiVolt I/O operation is
not available in 44-pin packages)
Pin compatible with low-voltage MAX 7000A and MAX 7000B
devices
Enhanced features available in MAX 7000E and MAX 7000S devices
Six pin- or logic-driven output enable signals
Two global clock signals with optional inversion
Enhanced interconnect resources for improved routability
Fast input setup times provided by a dedicated path from I/O
pin to macrocell registers
Programmable output slew-rate control
Software design support and automatic place-and-route provided by
Altera’s development system for Windows-based PCs and Sun
SPARCstation, and HP 9000 Series 700/800 workstations
EPM7160S
EPM7192S
3,200
3,750
160
192
10
12
104
124
6
7.5
3.4
4.1
2.5
3
3.9
4.7
149.3
125.0
Altera Corporation
EPM7256S
5,000
256
16
164
7.5
3.9
3
4.7
128.2

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