EP4CE55F29C8LN Altera, EP4CE55F29C8LN Datasheet - Page 143

• Manufacturer Part Number: EP4CE55F29C8LN
• Description: IC CYCLONE IV FPGA 55K 780FBGA
• Manufacturer: Altera
• Series: CYCLONE® IV Er

Specifications of EP4CE55F29C8LN

• Number Of Logic Elements/cells: 55856
• Number Of Labs/clbs: 3491
• Total Ram Bits: 2340000
• Number Of I /o: 374
• Voltage - Supply: 0.97 V ~ 1.03 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 780-FBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -

Chapter 6: I/O Features in Cyclone IV Devices
True Output Buffer Feature
Differential HSTL I/O Standard Support in Cyclone IV Devices
True Output Buffer Feature
Programmable Pre-Emphasis
© December 2010 Altera Corporation
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1
The differential HSTL I/O standard is used for the applications designed to operate in
0 V to 1.2 V, 0 V to 1.5 V, or 0 V to 1.8 V HSTL logic switching range. Cyclone IV
devices support differential HSTL-18, HSTL-15, and HSTL-12 I/O standards. The
differential HSTL input standard is available on GCLK pins only, treating the
differential inputs as two single-ended HSTL and only decoding one of them. The
differential HSTL output standard is only supported at the PLL#_CLKOUT pins using
two single-ended HSTL output buffers (PLL#_CLKOUTp and PLL#_CLKOUTn), with
the second output programmed to have opposite polarity. The standard requires two
differential inputs with an external reference voltage (VREF), as well as an external
termination voltage (VTT) of 0.5 × V
For differential HSTL signaling characteristics, refer to
Termination” on page 6–15
Figure 6–7 on page 6–15
Cyclone IV devices true differential transmitters offer programmable pre-emphasis—
you can turn it on or off. The default setting is on.
The programmable pre-emphasis boosts the high frequencies of the output signal to
compensate the frequency-dependant attenuation of the transmission line to
maximize the data eye opening at the far-end receiver. Without pre-emphasis, the
output current is limited by the V
transmitter. At high frequency, the slew rate may not be fast enough to reach full V
before the next edge; this may lead to pattern-dependent jitter. With pre-emphasis, the
output current is momentarily boosted during switching to increase the output slew
rate. The overshoot produced by this extra switching current is different from the
overshoot caused by signal reflection. This overshoot happens only during switching,
and does not produce ringing.
The Quartus II software allows two settings for programmable pre-emphasis
control—0 and 1, in which 0 is pre-emphasis off and 1 is pre-emphasis on. The default
setting is 1. The amount of pre-emphasis needed depends on the amplification of the
high-frequency components along the transmission line. You must adjust the setting
to suit your designs, as pre-emphasis decreases the amplitude of the low-frequency
component of the output signal.
shows the differential HSTL Class I and Class II interface.
and the
OD
Cyclone IV Device Datasheet
CCIO
specification and the output impedance of the
to which termination resistors are connected.
“Differential I/O Standard
Cyclone IV Device Handbook, Volume 1
chapter.
6–35
OD