EP4CE55F29C8LN Altera, EP4CE55F29C8LN Datasheet - Page 40

• Manufacturer Part Number: EP4CE55F29C8LN
• Description: IC CYCLONE IV FPGA 55K 780FBGA
• Manufacturer: Altera
• Series: CYCLONE® IV Er

Specifications of EP4CE55F29C8LN

• Number Of Logic Elements/cells: 55856
• Number Of Labs/clbs: 3491
• Total Ram Bits: 2340000
• Number Of I /o: 374
• Voltage - Supply: 0.97 V ~ 1.03 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 780-FBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -

3–4
Packed Mode Support
Address Clock Enable Support
Cyclone IV Device Handbook, Volume 1
Figure 3–1
Figure 3–1. Cyclone IV Devices byteena Functional Waveform
Note to
(1) For this functional waveform, New Data mode is selected.
When a byteena bit is deasserted during a write cycle, the old data in the memory
appears in the corresponding data-byte output. When a byteena bit is asserted
during a write cycle, the corresponding data-byte output depends on the setting
chosen in the Quartus
the old data at that location.
Cyclone IV devices M9K memory blocks support packed mode. You can implement
two single-port memory blocks in a single block under the following conditions:
■
■
Cyclone IV devices M9K memory blocks support an active-low address clock enable,
which holds the previous address value for as long as the addressstall signal is
high (addressstall = '1'). When you configure M9K memory blocks in dual-port
mode, each port has its own independent address clock enable.
Figure 3–2
feeds back to its input using a multiplexer. The multiplexer output is selected by the
address clock enable (addressstall) signal.
contents at a0
contents at a1
contents at a2
Each of the two independent block sizes is less than or equal to half of the M9K
block size. The maximum data width for each independent block is 18 bits wide.
Each of the single-port memory blocks is configured in single-clock mode. For
more information about packed mode support, refer to
page 3–7
q (asynch)
address
byteena
Figure
inclock
wren
rden
data
shows how the wren and byteena signals control the RAM operations.
shows an address clock enable block diagram. The address register output
3–1:
and
XXXX
XX
an
FFFF
“Single-Clock Mode” on page
doutn
FFFF
®
II software. The setting can either be the newly written data or
10
a0
FFFF
ABFF
ABCD
01
a1
FFCD
11
a2
3–15.
ABCD
Chapter 3: Memory Blocks in Cyclone IV Devices
ABFF
a0
(Note 1)
FFCD
© November 2009 Altera Corporation
ABFF
“Single-Port Mode” on
ABCD
a1
XXXX
XX
FFCD
a2
ABCD
Overview