EP4CE55F29C8LN Altera, EP4CE55F29C8LN Datasheet - Page 323

• Manufacturer Part Number: EP4CE55F29C8LN
• Description: IC CYCLONE IV FPGA 55K 780FBGA
• Manufacturer: Altera
• Series: CYCLONE® IV Er

Specifications of EP4CE55F29C8LN

• Number Of Logic Elements/cells: 55856
• Number Of Labs/clbs: 3491
• Total Ram Bits: 2340000
• Number Of I /o: 374
• Voltage - Supply: 0.97 V ~ 1.03 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 780-FBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -

Chapter 1: Cyclone IV Transceivers Architecture
Transceiver Functional Modes
Transceiver Functional Modes
Table 1–14. Transceiver Functional Modes for Protocol Implementation
Basic Mode
Figure 1–44. Transceiver Channel Datapath in Basic Mode
© December 2010 Altera Corporation
Basic
PCI Express
(PIPE)
GIGE
Serial RapidIO
XAUI
Deterministic
Latency
SDI
Functional Mode
Fabric
FPGA
Proprietary, SATA, V-
by-One, Display Port
PCIe Gen1 with PIPE
Proprietary, CPRI,
The Cyclone IV GX transceiver supports the functional modes as listed in
for protocol implementation.
The Cyclone IV GX transceiver channel datapath is highly flexible in Basic mode to
implement proprietary protocols. SATA, V-by-One, and Display Port protocol
implementations in Cyclone IV GX transceiver are supported with Basic mode.
Figure 1–44
Protocol
Interface
OBSAI
SRIO
XAUI
GbE
SDI
Phase
Comp
FIFO
Rx
shows the transceiver channel datapath supported in Basic mode.
wr_clk
Tx Phase
Comp
FIFO
rd_clk
Order-
Byte
Low latency PCS, transmitter in electrical idle, signal
detect at receiver, wider spread asynchronous SSC
PIPE ports, receiver detect, transmitter in electrical
idle, electrical idle inference, signal detect at receiver,
fast recovery, protocol-compliant word aligner and
rate match FIFO, synchronous SSC
Running disparity preservation, protocol-compliant
word aligner and rate match FIFO, recovered clock
port for applications such as Synchronous Ethernet
Protocol-compliant word aligner
Deskew FIFO, protocol-compliant word aligner and
rate match FIFO
TX PLL phase frequency detector (PFD) feedback,
registered mode FIFO, TX bit-slip control
High-speed SERDES, CDR
ing
serializer
Byte
De-
wr_clk
Byte Serializer
Transmitter Channel PCS
Decoder
8B/10B
rd_clk
Receiver Channel PCS
Key Feature
Match
FIFO
Rate
8B/10B Encoder
Deskew
FIFO
Cyclone IV Device Handbook, Volume 2
Aligner
Word
“Basic Mode” on
page 1–43
“PCI Express (PIPE)
Mode” on page 1–48
“GIGE Mode” on
page 1–54
“Serial RapidIO Mode”
on page 1–59
“XAUI Mode” on
page 1–61
“Deterministic Latency
Mode” on page 1–68
“SDI Mode” on
page 1–71
Deserial-
Reference
Transmitter Channel PMA
Receiver Channel PMA
izer
Serializer
Table 1–14
CDR
1–43