EP4CE55F29C8LN Altera, EP4CE55F29C8LN Datasheet - Page 348

• Manufacturer Part Number: EP4CE55F29C8LN
• Description: IC CYCLONE IV FPGA 55K 780FBGA
• Manufacturer: Altera
• Series: CYCLONE® IV Er

Specifications of EP4CE55F29C8LN

• Number Of Logic Elements/cells: 55856
• Number Of Labs/clbs: 3491
• Total Ram Bits: 2340000
• Number Of I /o: 374
• Voltage - Supply: 0.97 V ~ 1.03 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 780-FBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -

1–68
Deterministic Latency Mode
Figure 1–66. Transceiver Channel Datapath and Clocking when Configured in Deterministic Latency Mode
Note to
(1) High-speed recovered clock.
Cyclone IV Device Handbook, Volume 2
Fabric
FPGA
rx_clkout
tx_clkout
Figure 1–66
:
Deterministic Latency mode provides the transceiver configuration that allows no
latency uncertainty in the datapath and features to strictly control latency variation.
This mode supports non-bonded (×1) and bonded (×4) channel configurations, and is
typically used to support CPRI and OBSAI protocols that require accurate delay
measurements along the datapath. The Cyclone IV GX transceivers configured in
Deterministic Latency mode provides the following features:
■
■
■
■
Figure 1–66
deterministic latency mode.
registered mode phase compensation FIFO
receive bit-slip indication
transmit bit-slip control
PLL PFD feedback
Phase
Comp
FIFO
Rx
shows the transceiver channel datapath and clocking when configured in
wr_clk
Tx Phase
Comp
FIFO
rd_clk
Order-
Byte
ing
/2
serializer
Byte
De-
wr_clk
Byte Serializer
/2
Transmitter Channel PCS
Decoder
8B/10B
rd_clk
Receiver Channel PCS
Match
Rate
FIFO
Chapter 1: Cyclone IV Transceivers Architecture
8B/10B Encoder
Deskew
FIFO
© December 2010 Altera Corporation
Transceiver Functional Modes
Aligner
Word
low-speed recovered clock
Deserial-
Transmitter Channel PMA
Receiver Channel PMA
izer
Serializer
(1)
CDR
low-speed clock
high-speed
clock
CDR clock