EP4CE55F29C8LN Altera, EP4CE55F29C8LN Datasheet - Page 254

• Manufacturer Part Number: EP4CE55F29C8LN
• Description: IC CYCLONE IV FPGA 55K 780FBGA
• Manufacturer: Altera
• Series: CYCLONE® IV Er

Specifications of EP4CE55F29C8LN

• Number Of Logic Elements/cells: 55856
• Number Of Labs/clbs: 3491
• Total Ram Bits: 2340000
• Number Of I /o: 374
• Voltage - Supply: 0.97 V ~ 1.03 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 780-FBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -

9–8
Accessing Error Detection Block Through User Logic
Cyclone IV Device Handbook, Volume 1
1
The error detection circuit stores the computed 32-bit CRC signature in a 32-bit
register, which is read out by user logic from the core. The cycloneiv_crcblock
primitive is a WYSIWYG component used to establish the interface from the user
logic to the error detection circuit. The cycloneiv_crcblock primitive atom
contains the input and output ports that must be included in the atom. To access the
logic array, the cycloneiv_crcblock WYSIWYG atom must be inserted into your
design.
Figure 9–3
interface that the WYSIWYG atom enables in your design.
Figure 9–3. Error Detection Block Diagram
The user logic is affected by the soft error failure, so reading out the 32-bit CRC
signature through the regout should not be relied upon to detect a soft error. You
should rely on the CRC_ERROR output signal itself, because this CRC_ERROR output
signal cannot be affected by a soft error.
To enable the cycloneiv_crcblock WYSIWYG atom, you must name the atom for
each Cyclone IV device accordingly.
80 MHz Internal Chip Oscillator
shows the error detection block diagram in FPGA devices and shows the
(Saved in the Option Register)
SRAM
Bits
Pre-Computed CRC
Computation
(1 to 256 Factor)
CRC
Clock Divider
Error Detection
Logic
Chapter 9: SEU Mitigation in Cyclone IV Devices
Logic Array
© February 2010 Altera Corporation
V
CC
(Shown in BIDIR Mode)
CRC_ERROR
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