EP1S20F484C6N Altera, EP1S20F484C6N Datasheet - Page 163

• Manufacturer Part Number: EP1S20F484C6N
• Description: IC STRATIX FPGA 20K LE 484-FBGA
• Manufacturer: Altera
• Series: Stratix®r

Specifications of EP1S20F484C6N

• Number Of Logic Elements/cells: 18460
• Number Of Labs/clbs: 1846
• Total Ram Bits: 1669248
• Number Of I /o: 361
• Voltage - Supply: 1.425 V ~ 1.575 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 484-FBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -

Figure 2–75. Fast PLL & Channel Layout in the EP1S30 to EP1S80 Devices
Notes to
(1)
(2)
(3)
Altera Corporation
July 2005
Wire-bond packages support up to 624 Mbps.
See
There is a multiplexer here to select the PLL clock source. If a PLL uses this multiplexer to clock channels outside of
its bank quadrant, those clocked channels support up to 840 Mbps for “high” speed channels and 462 Mbps for
“low” speed channels as labeled in the device pin-outs at www.altera.com.
FPLL7CLK
Transmitter
Transmitter
Transmitter
Transmitter
FPLL8CLK
Table 2–38
Figure
Receiver
Receiver
Receiver
Receiver
CLKIN
CLKIN
2–75:
through
PLL 7
PLL 1
PLL 2
PLL 8
Fast
Fast
Fast
Fast
2–41
for the number of channels each device supports.
(3)
Channels in 20 Rows (2)
Channels in 20 Rows (2)
Channels in 20 Rows (2)
Channels in 20 Rows (2)
Up to 20 Receiver and
Up to 20 Receiver and
Up to 20 Receiver and
Up to 20 Receiver and
20 Transmitter
20 Transmitter
20 Transmitter
20 Transmitter
(3)
Stratix Device Handbook, Volume 1
Note (1)
PLL 10
PLL 4
PLL 3
PLL 9
Fast
Fast
Fast
Fast
Stratix Architecture
FPLL10CLK
Transmitter
Receiver
Transmitter
Receiver
CLKIN
CLKIN
Transmitter
Receiver
Transmitter
Receiver
FPLL9CLK
2–139