EP1S20F484C6N Altera, EP1S20F484C6N Datasheet - Page 648

• Manufacturer Part Number: EP1S20F484C6N
• Description: IC STRATIX FPGA 20K LE 484-FBGA
• Manufacturer: Altera
• Series: Stratix®r

Specifications of EP1S20F484C6N

• Number Of Logic Elements/cells: 18460
• Number Of Labs/clbs: 1846
• Total Ram Bits: 1669248
• Number Of I /o: 361
• Voltage - Supply: 1.425 V ~ 1.575 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 484-FBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -

10-Gigabit Ethernet
Figure 8–2. 10-Gigabit Ethernet Block Diagram
Notes to
(1)
(2)
(3)
8–4
Stratix Device Handbook, Volume 2
PHY
The reconciliation sublayer (RS) interfaces the serial MAC data stream and the parallel data of XGMII.
The XGMII extender sublayer (XGXS) extends the distance of XGMII when used with XUAI and provides the data
conversion between XGMII and XAUI.
The WAN interface sublayer (WIS) implements the OC-192 framing and scrambling functions.
Figure
Interface directly covered in this
application note
Interface indirectly covered in this
application note
Can be implemented in Altera PLDs
10GBASE-X
8–2:
PMD
PCS
PMA
8B/10B
MDI
10GBASE-R
XGXS (2)
RS (1)
XGXS
MAC
PMD
PCS
PMA
644.5 Mbps LVDS)
XSBI (16 Bits at
XGMII (32 Bits at 156.25 Mbps DDR 1.5-V HSTL)
XAUI (4 Bits at 3.125 Gbps PCML)
XGMII (32 Bits at 156.25 Mbps DDR 1.5-V HSTL)
64b/66b
8b/10b
MDI
8b/10b
10GBASE-W
WIS (3)
PMD
PMA
PCS
Altera Corporation
622.08 Mbps LVDS)
XSBI (16 Bits at
OC-192 Framing
July 2005
64b/66b