EP1S20F484C6N Altera, EP1S20F484C6N Datasheet - Page 650

• Manufacturer Part Number: EP1S20F484C6N
• Description: IC STRATIX FPGA 20K LE 484-FBGA
• Manufacturer: Altera
• Series: Stratix®r

Specifications of EP1S20F484C6N

• Number Of Logic Elements/cells: 18460
• Number Of Labs/clbs: 1846
• Total Ram Bits: 1669248
• Number Of I /o: 361
• Voltage - Supply: 1.425 V ~ 1.575 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 484-FBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -

Interfaces
8–6
Stratix Device Handbook, Volume 2
Functional Description
XSBI uses 16-bit LVDS data to interface between the PCS and the PMA
sublayer.
Figure 8–4. XSBI Functional Block Diagram
On the transmitter side, the transmit data (TX_D[15..0]) is output by
the PCS and input at the PMA using the transmitter clock (PMA_TXCLK),
which is derived from the PMA source clock (PMA_TXCLK_SRC). The
PMA source clock is generated from the PMA with its reference clock
(REFCLK). On the receiver side, the receiver data (RX_D[15..0]) is
output by the PMA and input at the PCS using the PMA-generated
receiver clock (PMA_RXCLK). The SYNC_ERR optional signal is sent to the
PCS by the PMA if the PMA fails to recover the clock from the serial data
stream.
The ratios for these two clocks and data are dependent on the type of PHY
used.
TX_D[15..0]
PMA_TXCLK
PMA_TXCLK_SRC
RX_D[15..0]
PMA_RXCLK
Table 8–1. XSBI Clock & Data Rates for WAN & LAN PHY
Parameter
Table 8–1
Figure 8–4
shows the rates for both PHY types.
Transmitter
Receiver
PCS
PCS
shows XSBI between these two sublayers.
WAN PHY
622.08
622.08
622.08
622.08
622.08
PMA_TXCLK_SRC
Sync_Err (optional)
PMA_TXCLK
PMA_RXCLK
TX_D[15..0]
RX_D[15..0]
REFCLK
644.53125
644.53125
644.53125
644.53125
644.53125
LAN PHY
Transmitter
Receiver
PMA
PMA
Altera Corporation
Mbps
Mbps
MHz
MHz
MHz
Unit
July 2005