EP1S20F484C6N Altera, EP1S20F484C6N Datasheet - Page 310

IC STRATIX FPGA 20K LE 484-FBGA

EP1S20F484C6N

Manufacturer Part Number
EP1S20F484C6N
Description
IC STRATIX FPGA 20K LE 484-FBGA
Manufacturer
Altera
Series
Stratix®r
Datasheet

Specifications of EP1S20F484C6N

Number Of Logic Elements/cells
18460
Number Of Labs/clbs
1846
Total Ram Bits
1669248
Number Of I /o
361
Voltage - Supply
1.425 V ~ 1.575 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
484-FBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-

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0
Clock Management
Section I–2
Chapter
1
November 2003, v2.2
October 2003, v2.1
July 2003, v2.0
Date/Version
Updated the
Updated the
Updated
Updated clock multiplication and division, spread spectrum, and Notes 1
and 8 in Table 1-3.
Updated inclk[1..0] port name in Table 1-4.
Updated ranges for EPLL post-scale and pre-scale dividers on page 1-9
Added 1.8V HSTL support for EPLL in Table 1-6 and 1-13.
New requirement to assert are set signal each PLL when it has to re-
acquire lock on either a new clock after loss of lock (page 1-16)
Corrected input port
chapter.
Updated
Updated text on jitter for spread spectrum on page 1-38.
Removed PLL specifications. See Chapter 4 of Volume 1.
Figure
clkloss
“Lock Detect”
“VCCG & GNDG”
1–14.
description in Table 1-9.
extswitch
Changes Made
section.
section.
to
Stratix Device Handbook, Volume 2
clkswitch
throughout this
Altera Corporation

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