EP1S20F484C6N Altera, EP1S20F484C6N Datasheet - Page 430

• Manufacturer Part Number: EP1S20F484C6N
• Description: IC STRATIX FPGA 20K LE 484-FBGA
• Manufacturer: Altera
• Series: Stratix®r

Specifications of EP1S20F484C6N

• Number Of Logic Elements/cells: 18460
• Number Of Labs/clbs: 1846
• Total Ram Bits: 1669248
• Number Of I /o: 361
• Voltage - Supply: 1.425 V ~ 1.575 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 484-FBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -

Stratix & Stratix GX I/O Standards
4–2
Stratix Device Handbook, Volume 2
3.3-V Low Voltage Transistor-Transistor Logic (LVTTL) -
EIA/JEDEC Standard JESD8-B
The 3.3-V LVTTL I/O standard is a general-purpose, single-ended
standard used for 3.3-V applications. The LVTTL standard defines the DC
interface parameters for digital circuits operating from a 3.0-V or 3.3-V
power supply and driving or being driven by LVTTL-compatible devices.
The LVTTL input standard specifies a wider input voltage range of
–0.5 V V
V. The LVTTL standard does not require input reference voltages or board
terminations.
Stratix and Stratix GX devices support both input and output levels for
3.3-V LVTTL operation.
Note to
(1)
PCI-X 1.0
AGP 1× and 2×
SSTL-3 Class I and II
SSTL-2 Class I and II
HSTL Class I
HSTL Class II
Differential HSTL
GTL
GTL+
LVDS
HyperTransport
technology
LVPECL
PCML
Differential SSTL-2
CTT
Table 4–1. I/O Standard Applications & Performance (Part 2 of 2)
These performance values are dependent on device speed grade, package type
(flip-chip or wirebond) and location of I/Os (top/bottom or left/right). See the
DC & Switching Characteristics chapter of the Stratix Device Handbook, Volume 1.
I/O Standard
Table
I
3.8 V. Altera allows an input voltage range of –0.5 V V
4–1:
PC/embedded systems
Graphics processors
SDRAM
DDR I SDRAM
QDR SRAM/SRAM/CSIX
QDR SRAM/SRAM/CSIX
Clock interfaces
Backplane driver
Pentium processor interface
Communications
Motherboard interfaces
PHY interface
Communications
DDR I SDRAM
Back planes and bus interfaces 200 MHz
Application
133 MHz
66 to 133 MHz
167 MHz
160 to 400 Mbps
150 to 225 MHz
150 to 250 MHz
150 to 225 MHz
200 MHz
133 to 200 MHz
840 Mbps
800 Mbps
840 Mbps
840 Mbps
160 to 400 Mbps
Altera Corporation
Performance
Note (1)
June 2006
I
4.1