EP1SGX40GF1020I6 Altera, EP1SGX40GF1020I6 Datasheet - Page 150

• Manufacturer Part Number: EP1SGX40GF1020I6
• Description: IC STRATIX GX FPGA 40K 1020-FBGA
• Manufacturer: Altera
• Series: Stratix® GXr

Specifications of EP1SGX40GF1020I6

• Number Of Logic Elements/cells: 41250
• Number Of Labs/clbs: 4125
• Total Ram Bits: 3423744
• Number Of I /o: 624
• Voltage - Supply: 1.425 V ~ 1.575 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 1020-FBGA
• Family Name: Stratix GX
• Number Of Logic Blocks/elements: 41250
• # I/os (max): 624
• Frequency (max): 5GHz
• Process Technology: SRAM
• Operating Supply Voltage (typ): 1.5V
• Logic Cells: 41250
• Ram Bits: 3423744
• Operating Supply Voltage (min): 1.425V
• Operating Supply Voltage (max): 1.575V
• Operating Temp Range: -40C to 100C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 1020
• Package Type: FC-FBGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Not Compliant

PLLs & Clock Networks
Figure 4–52. Clock Switchover Circuitry
Note to
(1)
4–84
Stratix GX Device Handbook, Volume 1
CLK0
CLK1
PFD: phase frequency detector.
Figure
4–52:
SMCLKSW
There are two possible ways to use the clock switchover feature.
■
■
MUXOUT
You can use automatic switchover circuitry for switching between
inputs of the same frequency. For example, in applications that
require a redundant clock with the same frequency as the primary
clock, the switchover state machine generates a signal that controls
the multiplexer select input on the bottom of
the secondary clock becomes the reference clock for the PLL.
You can use the clkswitch input for user- or system-controlled
switch conditions. This is possible for same-frequency switchover or
to switch between inputs of different frequencies. For example, if
inclk0 is 66 MHz and inclk1 is 100 MHz, you must control the
switchover because the automatic clock-sense circuitry cannot
monitor primary and secondary clock frequencies with a frequency
difference of more than ±20%. This feature is useful when clock
sources can originate from multiple cards on the backplane,
Sense
Enhanced PLL
Clock
n Counter
State Machine
Switch-Over
Δt
Figure
PFD
Altera Corporation
4–52. In this case,
February 2005
CLK0_BAD
CLK1_BAD
Active Clock
CLKLOSS
CLKSWITCH
FBCLK