EP1SGX40GF1020I6 Altera, EP1SGX40GF1020I6 Datasheet - Page 40

• Manufacturer Part Number: EP1SGX40GF1020I6
• Description: IC STRATIX GX FPGA 40K 1020-FBGA
• Manufacturer: Altera
• Series: Stratix® GXr

Specifications of EP1SGX40GF1020I6

• Number Of Logic Elements/cells: 41250
• Number Of Labs/clbs: 4125
• Total Ram Bits: 3423744
• Number Of I /o: 624
• Voltage - Supply: 1.425 V ~ 1.575 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 1020-FBGA
• Family Name: Stratix GX
• Number Of Logic Blocks/elements: 41250
• # I/os (max): 624
• Frequency (max): 5GHz
• Process Technology: SRAM
• Operating Supply Voltage (typ): 1.5V
• Logic Cells: 41250
• Ram Bits: 3423744
• Operating Supply Voltage (min): 1.425V
• Operating Supply Voltage (max): 1.575V
• Operating Temp Range: -40C to 100C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 1020
• Package Type: FC-FBGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Not Compliant

2–30
Stratix GX Device Handbook, Volume 1
Note to
(1)
PRBS 16-bit
PRBS 20-bit
Incremental 10-bit K28.5, K27.7, Data (00-FF
Incremental 20-bit K28.5, K27.7, Data (00-FF
High frequency
Low frequency
Mixed frequency
Table 2–9. BIST Data Output & Verifier Alignment Pattern (Part 2 of 2)
BIST Mode
This output repeats.
Table
2–9:
2
2
incremental), K28.0, K28.1,
K28.2, K28.3, K28.4, K28.6,
K28.7, K23.7, K30.7, K29.7
incremental), K28.0, K28.1,
K28.2, K28.3, K28.4, K28.6,
K28.7, K23.7, K30.7, K29.7
1010101010
0011111000
0011111010 or 1100000101
8
10
– 1
– 1
Stratix GX Clocking
The Stratix GX global clock can be driven by certain REFCLKB pins, all
transmitter PLL outputs, and all receiver PLL outputs. The REFCLKB pins
(except for transceiver block 0 and transceiver block 4) can drive inter-
transceiver and global clock lines as well as feed the transmitter and
receiver PLLs. The output of the transmitter PLL can only feed global
clock lines and the reference clock port of the receiver PLL.
Figures 2–26
connections as well as the global clock connections for the EP1SGX25F
and EP1SGX40G devices. For devices with fewer transceivers, ignore the
information about the unavailable transceiver blocks.
Output
and
(1)
(1)
2–27
x
x
8
10
are diagrams of the Inter-Transceiver line
+ x
+ x
Polynomials
7
7
+ x
+ 1
5
+ x
3
+ 1
1000000011111111
1111111111
0101111100 (K28.5)
0101111100 (K28.5)
Verifier Word Alignment Pattern
Altera Corporation
June 2006