EP1SGX40GF1020I6 Altera, EP1SGX40GF1020I6 Datasheet - Page 170

• Manufacturer Part Number: EP1SGX40GF1020I6
• Description: IC STRATIX GX FPGA 40K 1020-FBGA
• Manufacturer: Altera
• Series: Stratix® GXr

Specifications of EP1SGX40GF1020I6

• Number Of Logic Elements/cells: 41250
• Number Of Labs/clbs: 4125
• Total Ram Bits: 3423744
• Number Of I /o: 624
• Voltage - Supply: 1.425 V ~ 1.575 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 1020-FBGA
• Family Name: Stratix GX
• Number Of Logic Blocks/elements: 41250
• # I/os (max): 624
• Frequency (max): 5GHz
• Process Technology: SRAM
• Operating Supply Voltage (typ): 1.5V
• Logic Cells: 41250
• Ram Bits: 3423744
• Operating Supply Voltage (min): 1.425V
• Operating Supply Voltage (max): 1.575V
• Operating Temp Range: -40C to 100C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 1020
• Package Type: FC-FBGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Not Compliant

I/O Structure
Figure 4–64. Stratix GX IOE in DDR Input I/O Configuration
Notes to
(1)
(2)
(3)
4–104
Stratix GX Device Handbook, Volume 1
Column or Row
Interconnect
All input signals to the IOE can be inverted at the IOE.
This signal connection is only allowed on dedicated DQ function pins.
This signal is for dedicated DQS function pins only.
I/O Interconnect
Figure
[15..0]
4–64:
ioe_clk[7..0]
(1)
DQS Local
Bus (1), (2)
(1)
When using the IOE for DDR inputs, the two input registers clock double
rate input data on alternating edges. An input latch is also used within the
IOE for DDR input acquisition. The latch holds the data that is present
during the clock high times. This allows both bits of data to be
synchronous with the same clock edge (either rising or falling).
Figure 4–64
the DDR input timing diagram.
sclr
clkin
aclr/prn
Chip-Wide Reset
Enable Delay
Output Clock
shows an IOE configured for DDR input.
Input Register
Input Register
CLRN/PRN
D
ENA
CLRN/PRN
D
ENA
Input Register Delay
Input Pin to
Q
Q
Note (1)
D
ENA
CLRN/PRN
To DQS Local
Latch
Bus (3)
Q
VCCIO
Figure 4–65
Altera Corporation
VCCIO
Optional
PCI Clamp
February 2005
Bus-Hold
Circuit
Programmable
Pull-Up
Resistor
shows