EP1SGX40GF1020I6 Altera, EP1SGX40GF1020I6 Datasheet - Page 33

• Manufacturer Part Number: EP1SGX40GF1020I6
• Description: IC STRATIX GX FPGA 40K 1020-FBGA
• Manufacturer: Altera
• Series: Stratix® GXr

Specifications of EP1SGX40GF1020I6

• Number Of Logic Elements/cells: 41250
• Number Of Labs/clbs: 4125
• Total Ram Bits: 3423744
• Number Of I /o: 624
• Voltage - Supply: 1.425 V ~ 1.575 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 1020-FBGA
• Family Name: Stratix GX
• Number Of Logic Blocks/elements: 41250
• # I/os (max): 624
• Frequency (max): 5GHz
• Process Technology: SRAM
• Operating Supply Voltage (typ): 1.5V
• Logic Cells: 41250
• Ram Bits: 3423744
• Operating Supply Voltage (min): 1.425V
• Operating Supply Voltage (max): 1.575V
• Operating Temp Range: -40C to 100C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 1020
• Package Type: FC-FBGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Not Compliant

Altera Corporation
June 2006
Figure 2–19. Before & After the Channel Aligner
Rate Matcher
The rate matcher, which is available only in XAUI and GIGE modes,
consists of a 12-word deep FIFO buffer and a FIFO controller. The rate
matcher is bypassed when the device is not in XAUI or GIGE mode.
In a multi-crystal environment, the rate matcher compensates for up to a
100-ppm difference between the source and receiver clocks.
GIGE Mode
In the GIGE mode, the rate matcher adheres to the specifications in
clause 36 of the IEEE 802.3 documentation, for idle additions or removals.
The rate matcher performs clock compensation only on /I2/ ordered
sets, composing a /K28.5/+ followed by a /D16.2/-. The rate matcher
does not perform a clock compensation on any other ordered set
combinations. An /I2/ is added or deleted automatically based on the
number of words in the FIFO buffer. A 9’h19C is given at the control and
data ports when the FIFO is in an overflow or underflow condition.
Lane 0
Lane 0
Lane 0
Lane 0
Lane 0
Lane 0
Lane 0
Lane 0
K
K
K
K
K
K
K
K
K
K
K
K
K
K
R
R
R
R
R
K
R
K
A
A
A
A
A
R
A
R
K
K
K
K
K
A
K
Stratix GX Device Handbook, Volume 1
A
R
R
R
R
R
K
R
K
R
R
R
R
R
R
R
R
K
K
K
K
K
R
K
R
K
K
K
K
K
Stratix GX Transceivers
K
K
K
R
R
R
R
R
K
R
K
K
K
K
K
K
R
K
R
R
R
R
R
R
K
R
K
2–23
R
R