EP1SGX40GF1020I6 Altera, EP1SGX40GF1020I6 Datasheet - Page 34

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EP1SGX40GF1020I6

Manufacturer Part Number
EP1SGX40GF1020I6
Description
IC STRATIX GX FPGA 40K 1020-FBGA
Manufacturer
Altera
Series
Stratix® GXr
Datasheet

Specifications of EP1SGX40GF1020I6

Number Of Logic Elements/cells
41250
Number Of Labs/clbs
4125
Total Ram Bits
3423744
Number Of I /o
624
Voltage - Supply
1.425 V ~ 1.575 V
Mounting Type
Surface Mount
Operating Temperature
-40°C ~ 100°C
Package / Case
1020-FBGA
Family Name
Stratix GX
Number Of Logic Blocks/elements
41250
# I/os (max)
624
Frequency (max)
5GHz
Process Technology
SRAM
Operating Supply Voltage (typ)
1.5V
Logic Cells
41250
Ram Bits
3423744
Operating Supply Voltage (min)
1.425V
Operating Supply Voltage (max)
1.575V
Operating Temp Range
-40C to 100C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
1020
Package Type
FC-FBGA
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Number Of Gates
-
Lead Free Status / Rohs Status
Not Compliant

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2–24
Stratix GX Device Handbook, Volume 1
XAUI Mode
In XAUI mode, the rate matcher adheres to clause 48 of the IEEE 802.3ae
specification for clock rate compensation. The rate matcher performs
clock compensation on columns of /R/ (/K28.0/), denoted by //R//.
An //R// is added or deleted automatically based on the number of
words in the FIFO buffer.
8B/10B Decoder
The 8B/10B decoder converts the 10-bit encoded code group into 8-bit
data and 1 control bit. The 8B/10B decoder can be bypassed. The
following is a diagram of the conversion from a 10-bit encoded code
group into 8-bit data + 1-bit control.
Figure 2–20. 8B/10B Decoder Conversion
There are two optional error status ports available in the 8B/10B decoder,
rx_errdetect and rx_disperr.
ports from a given error. These status signals are aligned with the code
group in which the error occurred.
No errors
Invalid code groups
Disparity errors
Table 2–7. Error Signal Values
Types of Errors
Parallel data
MSB received last
9
j
h
8
H
7
g
7
G
6
rx_errdetect
8b-10b conversion
6
5
F
f
1’b0
1’b1
1’b1
E
4
5
i
Table 2–7
D
3
e
4
2
C
d
3
shows the values of the
1
B
c
2
LSB received first
0
A
b
1
rx_disperr
Altera Corporation
+
1’b0
1’b0
1’b1
a
0
ctrl
June 2006

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