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... Z8018x Family MPU User Manual UM005003-0703 ZiLOG W H ORLDWIDE EADQUARTERS T : 408.558.8500 • F ELEPHONE • 532 Race Street • 408.558.8300 • AX WWW , CA 95126-3432 OSE .Z LOG. I COM ...
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... Document Disclaimer © 2003 by ZiLOG, Inc. All rights reserved. Information in this publication concerning the devices, applications, or technology described is intended to suggest possible uses and may be superseded. ZiLOG, INC. DOES NOT ASSUME LIABILITY FOR OR PROVIDE A REPRESENTATION OF ACCURACY OF THE INFORMATION, DEVICES, OR TECHNOLOGY DESCRIBED IN THIS DOCUMENT. ZiLOG ...
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... Z80180/Z8S180/ Z8L180. These cores and base peripheral sets are used in a large family of ZiLOG products. Below is a list of ZiLOG products that use this class of processor, along with the associated processor family. This document is also the core user manual for the following products: ...
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... Presents the AC parameters for the Z8018x MPUs. Timing Diagrams Contains timing diagrams and standard test conditions for the Z8018x MPUs. Appendices The appendixes in this manual provide additional information applicable to the Z8018x family of ZiLOG MPUs: • Instruction set • Instruction summary table • ...
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Table of Contents Z80180, Z8S180, Z8L180 MPU Operation . . . . . . . . . . . . . . . . . . . .1 Features . . . . . . . . . . . ...
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Z8018x Family MPU User Manual vi Baud Rate Generator Clocked Serial I/O Port (CSI/ ...
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Flag . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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List of Figures Z80180, Z8S180, Z8L180 MPU Operation . . . . . . . . . . . . . . . . . . . .1 Figure 1. Figure 2. Figure 3. Figure 4. Figure 5. Figure 6. ...
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Z8018x Family MPU User Manual x Figure 21. SLEEP Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 35 Figure 22. ...
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Figure 49. TEND0 Output Timing Diagram . . . . . . . . . . . . . . . . . . .108 Figure 50. DMA Interrupt Request Generation . . . . . . . . . ...
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Z8018x Family MPU User Manual xii Software Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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List of Tables Z80180, Z8S180, Z8L180 MPU Operation . . . . . . . . . . . . . . . . . . . .1 Table 1. Table 2. Table 3. Table 4. Table 5. Table 6. ...
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Table 23. Table 24. Table 25. Software Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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Z8018x Family MPU User Manual xvi Table 43. Table 44. Table 45. Table 46. Table 47. Op Code Map . . . . . . . . . . . . . . . . . . . . . ...
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Z8018x Family MPU User Manual UM005003-0703 xv ...
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... On-Chip Interrupt Controller • On-Chip Clock Oscillator/Generator • Clocked Serial I/O Port • Code Compatible with ZiLOG Z80 CPU • Extended Instructions GENERAL DESCRIPTION Based on a microcoded execution unit and an advanced CMOS manufacturing technology, the Z80180, Z8S180, Z8L180 (Z8X180 8-bit MPU which provides the benefits of reduced system costs and low ...
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Z8018x Family MPU User Manual 2 on-chip memory management unit (MMU) with the capability of addressing memory. Reduced system costs are obtained by incorporating several key system functions on-chip with the CPU. These key functions ...
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XTAL 2 EXTAL 3 WAIT 4 BUSACK 5 BUSREQ 6 RESET 7 8 NMI 9 INT0 INT1 10 11 INT2 Z8X180 ...
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Z8018x Family MPU User Manual 4 10 INT0 INT1 11 INT2 A10 25 A11 ...
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NMI INT0 4 INT1 5 INT2 ...
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Z8018x Family MPU User Manual 6 Timing Phi Generator 16-bit Programmable A18/TOUT Reload Timers TXS Clocked Serial I/O RXS/CTS1 Port CKS MMU Address Buffer A0 Figure 4. UM005003-0703 Bus State Control Data Buffer – – A19 Z80180/Z8S180/Z8L180 Block ...
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PIN DESCRIPTION A0–A19. Address Bus (Output, Active High, 3-state). A0–A19 form a 20- bit address bus. The Address Bus provides the address for memory data bus exchanges MB, and I/O data bus exchanges 64K. The ...
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Z8018x Family MPU User Manual 8 D0–D7. Data Bus (Bidirectional, Active High, 3-state). D0-D7 constitute an 8-bit bidirectional data bus, used for the transfer of information to and from I/O and memory devices. The data bus enters the high impedance ...
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BUSREQ, and INT0 signals are inactive. The CPU acknowledges these interrupt requests with an interrupt acknowledge cycle. Unlike the acknowledgment for INT0, during this cycle neither the M1 or IORQ signals become Active. IORQ. I/O Request (Output, Active Low, 3-state). ...
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Z8018x Family MPU User Manual 10 RTS0. Request to Send 0 (Output, Active Low). This output is a programmable modem control signal for ASCI channel 0. RXA0, RXA1. Receive Data 0 and 1 (Inputs, Active High). These signals are the ...
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TOUT. Timer Out (Output, Active High). TOUT is the pulse output from PRT channel 1. This line is multiplexed with A18 of the address bus. TXA0, TXA1. Transmit Data 0 and 1 (Outputs, Active High). These signals are the transmitted ...
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Z8018x Family MPU User Manual 12 Table 2. Multiplexed Pins A18/TOUT CKA0/ CKA1/ CTS1 RXS/ ARCHITECTURE The Z8X180 combines a high performance CPU core with a variety of system and I/O resources useful in a broad range of applications. The ...
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Programmable Reload Timers (PRT, 2 channels) • Clock Serial I/O (CSIO) channel. Other Z8X180 family members (such as Z80183, Z80S183, Z80185/195) feature, in addition to these blocks, additional peripherals and are covered in their associated Product Specification Clock Generator ...
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Z8018x Family MPU User Manual 14 Central Processing Unit The CPU is microcoded to provide a core that is object code compatible with the Z80 CPU. It also provides a superset of the Z80 instruction set, including 8-bit multiply and ...
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OPERATION MODES The Z8X180 can be configured to operate like the Hitachi HD64180. This functionality is accomplished by allowing user control over the M1, IORQ, WR, and RD signals. The Operation Mode Control Register (OMCR), illustrated in Figure 5, determines ...
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Z8018x Family MPU User Manual 16 T1 Phi WR M1 Figure 6. M1TE (M1 Temporary Enable): This bit controls the temporary assertion of the M1 signal always read back and is set to 1 during ...
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T1 Phi IORQ RD WR Figure 7. I/O Read and Write Cycles with IOC = 1 Timing Diagram When IOC is , the timing of the IORQ and RD signals match the timing 0 required by the Z80 family of ...
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Z8018x Family MPU User Manual 18 Note: CPU Timing This section explains the Z8X180 CPU timing for the following operations: • Instruction (Op Code) fetch timing • Operand and data read/write timing • I/O read/write timing • Basic instruction (fetch ...
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The Op Code on the data bus is latched at the rising edge of T3 and the bus cycle terminates at the end of T3. T1 Phi – A0 A19 – WAIT M1 MREQ RD Figure 9. Op ...
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Z8018x Family MPU User Manual 20 Phi – A0 A19 – WAIT M1 MREQ RD Figure 10. Operand and Data Read/Write Timing The instruction operand and data read/write timing differs from Op Code fetch timing in two ways: ...
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Wait States (TW) are inserted as previously described for Op Code fetch cycles. Figure 11 illustrates the read/write timing without Wait States (Tw), while Figure 12 illustrates read/write timing with Wait States (TW). Read Cycle T1 T2 Phi – A0 ...
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Z8018x Family MPU User Manual 22 T1 Phi – A0 A19 – WAIT MREQ RD WR Figure 12. I/O Read/Write Timing I/O Read/Write operations differ from memory Read/Write operations in the following three ways: • The IORQ (I/O ...
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I/O Read Cycle T1 T2 Phi – A0 A19 I/O address – WAIT IORQ RD WR Figure 13. I/O Read/Write Timing Diagram Basic Instruction Timing An instruction may consist of a number of machine cycles including Op Code ...
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Z8018x Family MPU User Manual 24 1st Op Code Fetch Cycle Phi – A0 A19 PC (DDH) – MREQ RD WR Machine Cycle MC1 NOTE displacement g = register contents Figure ...
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The external bus is IDLE while the CPU computes the effective address. Finally, the computed memory location is written with the contents of the CPU register (g). RESET Timing Figure 15 depicts the Z8X180 hardware RESET timing. If the RESET ...
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Z8018x Family MPU User Manual 26 When the bus is released, the address (A0–A19), data (D0–D7), and control (MREQ, IORQ, RD, and WR) signals are placed in the high impedance state. Dynamic RAM refresh is not performed when the Z8X180 ...
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CPU Internal Operation T1 T1 Phi – A0 A19 – MREQ IORQ RD, WR BUSREQ BUSACK Figure 17. Bus Exchange Timing During CPU Internal Operation Wait State Generator To ease interfacing with slow memory and I/O devices, the ...
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Z8018x Family MPU User Manual 28 Dynamic RAM refresh is not performed during Wait States (TW) and thus system designs which use the automatic refresh function must consider the affects of the occurrence and duration of wait states (TW). Figure ...
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Bit MWI1 MWI0 MWI1 R/W R/W R/W Figure 19. Memory and I/O Wait State Insertion (DCNTL – DMA/Wait Control Register) The number of Wait States (TW) inserted in a specific cycle is the maximum of the number ...
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Z8018x Family MPU User Manual 30 inserted depending on the programmed value in IWI1 and IWI0. Refer to Table 4. Table 4. Wait State Insertion For external I/O registers IWI1 IWI0 accesses ...
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Also, the WAIT input is ignored during RESET. For example, if RESET is detected while the Z8X180 Wait State (TW), the Wait Stated cycle in progress is aborted, and the RESET sequence initiated. Thus, RESET has higher ...
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Z8018x Family MPU User Manual 32 • The HALT output pin is asserted Low • The external bus activity consists of repeated dummy fetches of the Op Code following the HALT instruction. Essentially, the Z80180 operates normally in HALT mode, ...
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HALT Op Code Fetch Cycle T1 T3 Phi INT1, NMI – A0 A19 HALT Op Code address HALT M1 MREQ RD Figure 20. HALT Timing Diagram SLEEP Mode SLEEP mode is entered by execution of the 2-byte SLP instruction. ...
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Z8018x Family MPU User Manual 34 • Data Bus, 3-state SLEEP mode is exited in one of two ways as described below. • RESET Exit from SLEEP mode. If the RESET input is held Low for at least six clock ...
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SLP 2nd Op Code Fetch Cycle Phi INT1, NMI – A0 A19 SLP 2nd Op Code address HALT M1 Figure 21. SLEEP Timing Diagram IOSTOP Mode IOSTOP mode is entered by setting the IOSTOP bit of the ...
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Z8018x Family MPU User Manual 36 Low Power Modes (Z8S180/Z8L180 only) The following section is a detailed description of the enhancements to the Z8S180/L180 from the standard Z80180 in the areas of STANDBY, IDLE and STANDBY QUICK RECOVERY modes. Add-On ...
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Table 5. Power-Down Modes (Z8S180/Z8L180-Class Processors Only) Power- Down On-Chip Modes CPU Core I/O SLEEP Stop Running I/O STOP Running Stop SYSTEM Stop Stop STOP IDLE † Stop Stop STANDBY † Stop Stop † IDLE and STANDBY modes are only ...
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Z8018x Family MPU User Manual 38 1. Set bits 6 and Set the I/O STOP bits (bit 5 of ICR, I/O Address = 3. Execute the SLEEP instruction. When the device is in STANDBY mode, it performs ...
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If the BREXT bit of the CPU Control Register (CCR) is cleared, asserting the BUSREQ does not cause the Z8S180/Z8L180-class processors to exit STANDBY mode. If STANDBY mode is exited because of a reset or an external interrupt, the Z8S180/Z8L180-class ...
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Z8018x Family MPU User Manual 40 If the Global Interrupt Enable Flag IEF1 is set to 1, and if an interrupt source is enabled in the ITC, asserting the corresponding interrupt input causes the Z8S180/Z8L180-class processors to exit STANDBY mode. ...
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All control signals are asserted eight clock cycles after the exit conditions are gathered. STANDBY-QUICK RECOVERY Mode STANDBY-QUICK RECOVERY mode is an option offered in STANDBY mode to reduce the ...
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Z8018x Family MPU User Manual 42 To avoid address conflicts with external I/O, the Z8X180 internal I/O addresses can be relocated on 64-byte boundaries within the bottom 256 bytes of the 64KB I/O address space. I/O Control Register (ICR) ICR ...
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IOA7 — IOA6 = 1 1 IOA7 — IOA6 = 1 0 IOA7 — IOA6 = 0 1 IOA7 — IOA6 = 0 0 Figure 22. I/O Address Relocation Internal I/O Registers Address Map The internal I/O register addresses are ...
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Z8018x Family MPU User Manual 44 address to OTDMR and TSTIO (see Instruction Set). When writing to an internal I/O register, the same I/O write occurs on the external bus. However, the duplicate external I/O write cycle exhibits internal I/O ...
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Table 6. I/O Address Map for Z80180-Class Processors Only (Continued) Register Timer Data Register Data Register Reload Register Reload Register Timer Control Register Reserved Data Register Ch 1 ...
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Z8018x Family MPU User Manual 46 Table 6. I/O Address Map for Z80180-Class Processors Only (Continued) Register DMA DMA Source Address Register Ch 0L DMA Source Address Register Ch 0H DMA Source Address Register Ch 0B DMA Destination Address Register ...
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Table 6. I/O Address Map for Z80180-Class Processors Only (Continued) Register INT IL Register (Interrupt Vector Low Register) INT/TRAP Control Register Reserved Refresh Refresh Control Register Reserved MMU MMU Common Base Register MMU Bank Base Register MMU Common/Bank Area Register ...
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Z8018x Family MPU User Manual 48 Table 7. I/O Address Map (Z8S180/Z8L180-Class Processors Only) Register ASCI ASCI Control Register ASCI Control Register ASCI Control Register ASCI Control Register ...
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Table 7. I/O Address Map (Z8S180/Z8L180-Class Processors Only) (Continued) Register Timer Data Register Data Register Reload Register Reload Register Timer Control Register Reserved Data Register ...
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Z8018x Family MPU User Manual 50 Table 7. I/O Address Map (Z8S180/Z8L180-Class Processors Only) (Continued) Register DMA DMA Source Address Register Ch 0L DMA Source Address Register Ch 0H DMA Source Address Register Ch 0B DMA Destination Address Register Ch ...
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Table 7. I/O Address Map (Z8S180/Z8L180-Class Processors Only) (Continued) Register INT IL Register (Interrupt Vector Low Register) INT/TRAP Control Register Reserved Refresh Refresh Control Register Reserved MMU MMU Common Base Register MMU Bank Base Register MMU Common/Bank Area Register I/O ...
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Z8018x Family MPU User Manual 52 Clock Multiplier Register (CMR: 1EH) (Z8S180/L180-Class Processors Only) Bit 7 Bit/Field X2 R/W R/W Reset 0 Note Read W = Write X = Indeterminate ? = Not Applicable Bit Position Bit/Field R/W ...
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CPU Control Register (CCR: 1FH) (Z8S180/L180-Class Processors Only) Bit 7 6 Bit/Field Clock STAND Divide BY/ IDLE Enable R/W R/W R/W Reset 0 0 Note Read W = Write X = Indeterminate ? = Not Applicable Bit Position ...
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Z8018x Family MPU User Manual 54 Bit Position Bit/Field 2 LNIO 1 LNCPUCTL 0 LNAD/ DATA Memory Management Unit (MMU) The Z8X180 features an on-chip MMU which performs the translation of the CPU 64KB (16-bit addresses address space into a ...
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Common Common Area 1 Area 1 Bank Area Bank Area Common Area 0 Figure 23. Logical Address Mapping Examples Logical to Physical Address Translation Figure 24 illustrates an example in which the three logical address space portions are mapped into ...
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Z8018x Family MPU User Manual 56 FFFFH Common Area 1 Bank Area Common Area 0 0000H Logical Address Space Figure 24. MMU Block Diagram The MMU block diagram is depicted in Figure 25. The MMU translates internal 16-bit logical addresses ...
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Whether address translation (Figure 26) takes place depends on the type of CPU cycle as follows. • Memory Cycles Address Translation occurs for all memory access cycles including instruction and operand fetches, memory data reads and writes, hardware interrupt vector ...
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Z8018x Family MPU User Manual 58 • MMU Common/Bank Area Register (CBAR) • MMU Common Base Register (CBR) • MMU Bank Base Register (BBR) CBAR is used to define the logical memory organization, while CBR and BBR are used to ...
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MMU Common/Bank Area Register MMU Common/Bank Area Register Figure 28. Logical Space Configuration (Example) Family MPU User Manual FFFFH Common Area 1 ...
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Z8018x Family MPU User Manual 60 MMU Register Description MMU Common/Bank Area Register (CBAR) CBAR specifies boundaries within the Z8X180 64KB logical address space for up to three areas; Common Area 0, Bank Area and Common Area 1. MMU Common/Bank ...
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MMU Common Base Register (CBR) CBR specifies the base address (on 4K boundaries) used to generate a 20- bit physical address for Common Area 1 accesses. All bits of CBR are reset to 0 during RESET. MMU Common Base Register ...
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Z8018x Family MPU User Manual 62 MMU Bank Base Register (BBR) BBR specifies the base address (on 4KB boundaries) used to generate a 20-bit physical address for Bank Area accesses. All bits of BBR are reset to during RESET. 0 ...
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MMU and RESET During RESET, all bits of the CA field of CBAR are set to of the BA field of CBAR, CBR and BBR are reset to address space corresponds directly with the first 64KB of the 1024KB . ...
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Z8018x Family MPU User Manual 64 MMU Common/ Bank Area Register D7 — D4 MMU Common/ Bank Area Register D3 — D0 MMU Common Base Reg. MMU Bank Base Reg (512 k ...
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Packages not containing an A19 pin or situations using TOUT Note: instead of A18 yield an address capable of only addressing 512K of physical space. Interrupts The Z8X180 CPU has twelve interrupt sources, 4 external and 8 internal, with fixed ...
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Z8018x Family MPU User Manual 66 Function Interrupt Vector High Interrupt Vector Low Interrupt/Trap Control Interrupt Enable Flag 1,2 IEF1, IEF2 El and DI Interrupt Vector Register (I) Mode 2 for INT0 external interrupt, INT1 and INT2 external interrupts, and ...
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IL is initialized to during RESET. 00H Interrupt Vector Low Register (IL: 33H) Bit 7 6 Bit/Field IL7 IL6 R/W R/W R/W Reset 00H 00H Note Read W = ...
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Z8018x Family MPU User Manual 68 INT/TRAP Control Register (ITC: 34H) Bit 7 Bit/Field TRAP R/W R/W Reset 0 Note Read W = Write X = Indeterminate ? = Not Applicable Bit Position Bit/Field R/W 7 TRAP R/W ...
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If IEF1 is , all maskable interrupts are disabled. IEF1 can be reset to 0 the DI (Disable Interrupts) instruction and set to Interrupts) instruction. The purpose of IEF2 is to correctly manage the occurrence of NMI. During NMI, the ...
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Z8018x Family MPU User Manual 70 Table 8. CPU Operation LID A, R TRAP Interrupt The Z8X180 generates a non-maskable (not affected by the state of IEF1) TRAP interrupt when an undefined Op Code fetch occurs. ...
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PC-1. If UFO is equal to the stacked PC-2. Bus Release cycle, Refresh cycle, DMA cycle, and WAIT cycle cannot be inserted just after TTP state which is inserted for TRAP interrupt sequence. Figure depicts TRAP Timing - 2nd ...
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Z8018x Family MPU User Manual 72 3rd Op Code Fetch Cycle Phi – A0 A19 PC – Undefined Op Code MI MREQ RD WR Figure 33. External Interrupts The Z8X180 features four external hardware interrupt ...
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DMAC operation is suspended by the clearing of the DME (DMA Main Enable) bit in DCNTL. 2. The PC is pushed onto the stack. 3. The contents of IEF1 are copied to IEF2. This saves the interrupt reception state ...
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Z8018x Family MPU User Manual 74 Figure 34. Last MC Phi NMI – A0 A19 – MREQ RD WR UM005003-0703 ® EF1 EF2 ® 0 EF1 Main ® PCH (SP-1) Program ® PCL (SP-2) NMI ¬ EF1 ...
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Figure 35. NMI Timing INT0 - Maskable Interrupt Level 0 The next highest priority external interrupt after NMI is INT0. INT0 is sampled at the falling edge of the clock state prior the last machine ...
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Z8018x Family MPU User Manual 76 Phi INT0 – A0 A19 M1 MREQ RD WR IORQ – Note: Figure 36. INT0 Mode 1 When INT0 is received, the PC is stacked and instruction execution restarts at logical address ...
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The interrupt service routine normally terminates with the EI (Enable Interrupts) instruction followed by the RETI (Return from Interrupt) instruction, to reenable the interrupts. Figure 37 depicts the use of INT0 (Mode 1) and RETI for ...
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Z8018x Family MPU User Manual 78 Phi INT0 – A0 A19 M1 MREQ IORQ RD WR – Figure 38. INT0 Mode 2 This method determines the restart address by reading the contents of a table residing in ...
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The vector table address is located on 256 byte boundaries in the 64KB logical address space programmed in the 8-bit Interrupt Vector Register (1). Figure 39 depicts the INT0 Mode 2 Vector acquisition. 16-bit Vector Interrupt Vector 8-bit on Data ...
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Z8018x Family MPU User Manual 80 Last Phi INT0 – A0 A19 M1 MREQ IORQ RD WR – Figure 40. INT1, INT2 The operation of external interrupts INT1 and INT2 is a vector mode ...
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TRAP). As depicted in Figure 41, the low-order byte of the vector table address has the most significant three bits of the software programmable IL register while the least ...
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Z8018x Family MPU User Manual 82 individual I/O (PRT, DMAC, CSI/O, ASCI) control register. The lower vector of INT1 INT2 and internal interrupt are summarized in Table 9. Table 9. Interrupt Source Priority INT1 Highest INT2 PRT channel 0 PRT ...
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Interrupt Sources During RESET Interrupt Vector Register (I) All bits are reset to . Because logical address 0000H and internal interrupts) overlap with fixed restart interrupts like RESET (0), NMI ( ), INT0 Mode 1 ( 0066H ...
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Z8018x Family MPU User Manual 84 Return from Subroutine (RETI) Instruction Sequence When the the RETI instruction sequence. The Z8X180 then refetches the RETI instruction with four T-states in the peripherals time to decode that cycle (See Figure 42). This ...
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Z8X180. Figure 43 illustrates the INT1, INT2 and internal interrupts timing. Table 10. RETI Control Signal States Machine Cycle States Address Data 1 T1-T3 1st EDH Op Code 2 TI-T3 2nd 4DH Op Code 3 T1 Don't 3-state Care 4 ...
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Z8018x Family MPU User Manual 86 INT1, INT2, internal interrupt acknowledge cycle Last Phi INT1,2 – A0 A19 M1 MREQ IORQ RD WR – MC: Machine Cycle Figure 43. Dynamic RAM Refresh Control The ...
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Refresh cycles may be programmed to be either two or three clock cycles in duration by programming the REFW (Refresh Wait) bit in the Refresh Control Register (RCR). The external WAIT input and the internal Wait State generator are not ...
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Z8018x Family MPU User Manual 88 Refresh Control Register (RCR) The RCR specifies the interval and length of refresh cycles, while enabling or disabling the refresh function. Refresh Control Register (RCR: 36H) Bit 7 Bit/Field REFE R/W R/W Reset 1 ...
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Table 11. DRAM Refresh Intervals Insertion CYC1 CYC0 Interval states states states states * Calculated interval Refresh Control And RESET After RESET, based on the initialized value of ...
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Z8018x Family MPU User Manual 90 3. Refresh cycles are suppressed during SLEEP mode refresh cycle is requested during SLEEP mode, the refresh cycle request is internally latched (until replaced with the next refresh request). The latched refresh ...
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DREQ Input Level- and edge-sense DREQ input detection are selectable. TEND Output Used to indicate DMA completion to external devices. • Transfer Rate Each byte transfer occurs every 6 clock cycles. Wait States can be inserted in DMA cycles ...
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Z8018x Family MPU User Manual 92 Channel 0 • SAR0–Source Address Register • DAR0–Destination Address Register • BCR0–Byte Count Register Channel 1 • MAR1–Memory Address Register • IAR1–I/O Address Register • BCR1–Byte Count Register The two channels share the following ...
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Internal Address/Data Bus DMA Status DMA Source Address Register : DSTAT (8) Register ch0 : SAR0 (20) DMA Destination Address DMA Mode Register ch0 : DAR0 (20) Register : DMODE (8) DMA Byte Count DMA/WAIT Control Register ch0 : BCR0 ...
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Z8018x Family MPU User Manual 94 DMA Destination Address Register Channel 0 (DAR0 I/O Address = 23H to 25H) Specifies the physical destination address for channel 0 transfers. The register contains 20 bits and can specify up to 1024KB memory ...
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DMA Status Register (DSTAT) DSTAT is used to enable and disable DMA transfer and DMA termination interrupts. DSTAT also determines DMA transfer status, that is, completed or in progress. DMA Status Register (DSTAT: 30H) Bit 7 6 Bit/Field DE1 DE0 ...
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Z8018x Family MPU User Manual 96 Bit Position Bit/Field R/W 6 DE0 R/W 5 DWE1 W 4 DWE0 W 3 DIE1 R/W 2 DIE0 UM005003-0703 Value Description Enable Channel 0 — When DE0 = 1 and DME = 1, channel ...
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Bit Position Bit/Field R/W 0 DME R DMA Mode Register (DMODE) DMODE is used to set the addressing and transfer mode for channel 0. DMA Mode Register (DMODE: 31H) Bit 7 6 Bit/Field ? R/W ? Reset ? Note: R ...
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Z8018x Family MPU User Manual 98 Bit Position Bit/Field R/W – SM1 MMOD R/W Table 12. DM1 UM005003-0703 Value Description Source Mode Channel — Specifies whether the source for channel 0 transfers ...
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Table 13. Channel 0 Source SM1 SM0 Table 14 describes all DMA TRANSFER mode combinations of DM0 DM1, SM0 SM1. Because I/O to/from I/O transfers are not implemented, 12 combinations are available. ...
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Z8018x Family MPU User Manual 100 Table 14. DM1 DM0 SM1 SM0 Transfer Mode Note: *: includes memory mapped I/O. DMA/WAIT Control Register (DCNTL) ...
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DMA/WAIT Control Register (DCNTL: 32H) Bit 7 6 Bit/Field MWI1 MWI0 R/W R/W R/W Reset 0 0 Note Read W = Write X = Indeterminate ? = Not Applicable Bit Position Bit/Field R/W – – MWI1 ...
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Z8018x Family MPU User Manual 102 Table 15. DIM1 DIM0 Transfer Mode DMA I/O Address Register Ch. 1 (IAR1B: 2DH) (Z8S180/L180-Class Processor Only) Bit 7 6 Bit/Field R/W R/W R/W Reset 0 Note Read ...
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Bit Position Bit/Field R/W 2-0 R/W DMA Register Description Bit 7 This bit must be set to 1 only when both DMA channels are set to take their requests from the same device. If this bit is 1 (it resets ...
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Z8018x Family MPU User Manual 104 Bits 5–3 Reserved. Must be 0. Bits 2–0 With DIM1, bit 1 of DCNTL, these bits control which request is presented to DMA channel 1, as described below: DIM1 IAR18–16 Request Routed to DMA ...
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In addition, the operation of channel 0 DMA with the on-chip ASCI (Asynchronous Serial Communication Interface) as well as Channel 1 DMA are described. Memory to Memory—Channel 0 For memory to/from memory transfers, the external DREQ0 input is not used ...
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Z8018x Family MPU User Manual 106 Address Figure 46. To initiate memory to/from memory DMA transfer for channel 0, perform the following operations. 1. Load the memory source and destination address into SAR0 and DAR0 2. Specify memory to/from memory ...
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Memory to I/O (Memory Mapped I/O) — Channel 0 For memory to/from I/O (and memory to/from memory mapped I/O) the DREQ0 input is used to time the DMA transfers. In addition, the TEND0 (Transfer End) output is used to indicate ...
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Z8018x Family MPU User Manual 108 rising edge of the clock prior which time the DMA operation (re)starts. Figure 48 depicts the edge-sense DMA timing. DMA Write Cycle Tw Phi ** DREQ0 Figure 48. During the transfers ...
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I/O. transfers, the CKA0/DREQ0 pin automatically functions as input pin or output pin even if it has been programmed as output pin for CKA0. And the CKA1/TEND0 pin functions as an input or an output pin for TEND0 ...
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Z8018x Family MPU User Manual 110 DREQ0 for ASCI transmission and reception respectively. To initiate memory to/from ASCI DMA transfer, perform the following operations: 1. Load the source and destination addresses into SAR0 and DAR0 Specify the I/O (ASCI) address ...
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Specify memory « I/O transfer mode and address increment/ decrement in the SM0, SM1, DM0 and DM1 bits of DMODE. 3. Load the number of bytes to transfer in BCR0 4. The DMA request sense mode (DMS0 bit in ...
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Z8018x Family MPU User Manual 112 4. Specify whether DREQ1 is level- or edge- sense in the DMS1 bit in DCNTL. 5. Enable or disable DMA termination interrupt with the DIE1 bit in DSTAT. 6. Program DE1 = and the ...
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Ti state. DMAC Channel Priority For simultaneous DREQ0 and DREQ1 requests, channel 0 has priority over channel 1. When channel 0 is performing a memory to/from memory transfer, ...
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Z8018x Family MPU User Manual 114 DMAC Internal Interrupts Figure 50 illustrates the internal DMA interrupt request generation circuit. DE1 DIE1 DE0 DIE0 Figure 50. DE0 and DE1 are automatically cleared to completion (byte count is channel 1, respectively. They ...
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If the falling edge of NMI occurs before the falling clock of the state prior to T3 (T2 or Tw) of the DMA write cycle, the DMAC is suspended and the CPU starts the NMI response at the end of ...
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Z8018x Family MPU User Manual 116 The key functions for ASCI on Z80180, Z8S180 and Z8L180 class processors are listed below. Each channel is independently programmable. • Full-duplex communication • 8-bit data length • Program controlled 9th data ...
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ASCI Transmit Data Register TDR0 TXA0 ASCI Transmit Shift Register TSR0 ASCI Receive Data Register RDR0 RXA0 ASCI Receive Shift Register RSR0 (8) ASCI Control Register A ch ...
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Z8018x Family MPU User Manual 118 When transmission is completed, the next byte (if available) is automatically loaded from TDR into TSR and the next transmission starts data is available for transmission, TSR idles by outputting a continuous ...
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ASCI Receive Shift Register 0,1(RSR0, 1) This register receives data shifted in on the RXA pin. When full, data is automatically transferred to the ASCI Receive Data Register (RDR empty. If RSR is not empty when the ...
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Z8018x Family MPU User Manual 120 , data can be written into the ASCII Receive Data Register, and the data 0 can be read. ASCI Status Register 0, 1 (STAT0, 1) Each channel status register allows interrogation of ASCI communication, ...
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Bit Position Bit/Field R RIE R/W 2 DCD0 R 1 TDRE R Value Description Parity Error — set to 1 when a parity error is detected on an incoming data byte ...
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Z8018x Family MPU User Manual 122 Bit Position Bit/Field R/W 0 TIE R/W UM005003-0703 Value Description Transmit Interrupt Enable — TIE must be set enable ASCI transmit interrupt requests. If TIE interrupt is requested ...
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ASCI Control Register A0, 1 (CNTLA0, 1) Each ASCI channel Control Register A configures the major operating modes such as receiver/transmitter enable and disable, data format, and multiprocessor communication mode. ASCI Status Register 1 (STAT1: 05H) Bit 7 6 Bit/Field ...
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Z8018x Family MPU User Manual 124 Bit Position Bit/Field R RIE R/W 2 CTS1E R/W 1 TDRE R 0 TIE R/W UM005003-0703 Value Description Framing Error — receive data byte frame is delimited by ...
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ASCI Control Register A0, 1 (CNTLA0, 1) Each ASCI channel Control Register A configures the major operating modes such as receiver/transmitter enable and disable, data format, and multiprocessor communication mode. ASCI Control Register A 0 (CNTLA0: 00H) Bit 7 6 ...
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Z8018x Family MPU User Manual 126 Bit Position Bit/Field R R R/W RTS0 4 R/W 3 MPBR/ R/W EFR UM005003-0703 Value Description Receiver Enable — When RE is set to 1, the ASCI receiver is enabled. ...
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Bit Position Bit/Field R/W – – MOD2 0 R/W Value Description ASCI Data Format Mode — These bits program the ASCI data format as follows. MOD2 0: 7 bit data 1: 8 bit data MOD1 ...
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Z8018x Family MPU User Manual 128 ASCI Control Register A 1 (CNTLA1: 01H) Bit 7 Bit/Field MPE R/W R/W Reset Read W = Write X = Indeterminate ? = Not Applicable Bit Position Bit/Field R/W 7 MPE ...
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Bit Position Bit/Field R R/W 4 CKA1D R/W 3 MPBR/ R/W EFR Value Description Transmitter Enable — When TE is set to 1, the ASCI transmitter is enabled. When TE is reset to 0, the transmitter is disabled ...
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Z8018x Family MPU User Manual 130 Bit Position Bit/Field R/W – – MOD2 0 R/W UM005003-0703 Value Description ASCI Data Format Mode — These bits program the ASCI data format as follows. MOD2 0: 7 ...
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Table 17. Data Formats MOD2 MOD1 MOD0 Data Format Start + 7 bit data + 1 stop Start + 7 bit date + 2 Stop Start + 7 bit data + ...
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Z8018x Family MPU User Manual 132 ASCI Control Register B 0 (CNTLB0: 02H) ASCI Control Register B 1 (CNTLB1: 03H) Bit 7 Bit/Field MPBT R/W R/W Reset X Note Read W = Write X = Indeterminate ? = ...
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Bit Position Bit/Field R/W 5 CTS/PS R/W 4 PEO R R/W – – SS2 0 R/W The external ASCI channel 0 data clock pins are multiplexed with DMA control lines (CKA0/DREQ and CKA1/TEND0). During RESET, these ...
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Z8018x Family MPU User Manual 134 pins are initialized as ASCI data clock inputs. If SS2, SS1 and SS0 are reprogrammed (any other value than SS2, SS1, SS0 = become ASCI data clock inputs. However, if DMAC channel 0 is ...
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ASCI0 Extension Control Register (I/O Address: 12H) (Z8S180/L180-Class Processors Only) Bit 7 6 Bit/Field RDRF DCD0 Int Disable Inhibit R/W R/W R/W Reset 0 0 Note Read W = Write X = Indeterminate ? = Not Applicable Bit ...
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Z8018x Family MPU User Manual 136 Bit Position Bit/Field R/W 0 Send R/W Break Each ASCI channel control register B configures multiprocessor mode, parity and baud rate selection. ASCI1 Extension Control Register (I/O Address: 13H) (Z8S180/L180-Class Processors Only) Bit 7 ...
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Bit Position Bit/Field R/W 2 Break R/W Feature Enable 1 Break R/W Detect (RO) 0 Send R/W Break Each ASCI channel control register B configures multiprocessor mode, parity and baud rate selection. ASCI0 Time Constant Low Register (I/O Address: 1AH) ...
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Z8018x Family MPU User Manual 138 ASCI1 Time Constant Low Register (I/O Address: 1CH) (Z8S180/L180-Class Processors Only) Bit 7 R/W R/W Reset 0 Note Read W = Write X = Indeterminate ? = Not Applicable ASCI1 Time Constant ...
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The error flags (PE, FE, and OVRN bits) are also held at DCD0 input goes Low, these bits do not resume normal operation until the status register (STAT0, is read. This first read of (STAT0, while enabling normal operation, still ...
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Z8018x Family MPU User Manual 140 Phi WR RTS0 Flag RTS0 Pin Figure 54. Figure 55 illustrates the ASCI interrupt request generation circuit. DCD0 RDRF0 OVRN0 PE0 FE0 RDRF1 OVRN1 PE1 FE1 Figure 55. UM005003-0703 I/O Instruction T1 RTS0 Timing ...
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ASCI to/from DMAC Operation Operation of the ASCI with the on-chip DMAC channel 0 requires that the DMAC be correctly configured to use the ASCI flags as DMA request signals. ASCI and RESET During RESET, the ASCI status and control ...
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Z8018x Family MPU User Manual 142 Table 19. Sampling Prescaler Rate Divide SS2 SS1 SS0 Divide PS Ratio DR Rate ¸ ...
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Table 19. ASCI Baud Rate Selection (Continued) Sampling Prescaler Rate Baud Rate Divide SS2 SS1 SS0 Divide PS Ratio DR Rate ¸ 30 ...
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Z8018x Family MPU User Manual 144 a common baud rate 512 Kbps to be selected. The BRG can also be disabled in favor of an external clock on the CKA pin. The Receiver and Transmitter subsequently divide ...
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CNTLB register, as described in Table 21. Table 21. 2^ss Values ss2 ss1 ss0 2^ ...
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Z8018x Family MPU User Manual 146 causes for an ASCI Receive interrupt (PE, FE, OVRN, and for ASCI0, DCD) continue to request RX interrupt if the RIE bit is 1. The Rx DMA request is inhibited ...
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TXS CSI/O Transmit/Receive Data Register: RXS TRDR (8) CSI/O Control Register: CNTR (8) Interrupt Request Figure 57. CSI/O Registers Description CSI/O Control/Status Register (CNTR: I/O Address 0AH) CNTR is used to monitor CSI/O status, enable and disable the CSI/O, enable ...
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Z8018x Family MPU User Manual 148 Bit Position Bit/Field R EIE R R/W UM005003-0703 Value Description End Flag — set the CSI/O to indicate completion of an 8-bit data ...
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Bit Position Bit/Field R R/W – – SS2 0 R/W CSI/O Transmit/Receive Data Register (TRDR: I/O Address = 0BH). TRDR is used for both CSI/O transmission and reception. Thus, the system design must insure that the ...
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Z8018x Family MPU User Manual 150 CSI/O Transmit/Receive Register (TRDR: 0BH) Bit 7 Bit/Field R/W Reset Note Read W = Write X = Indeterminate ? = Not Applicable Table 22. SS2 ...
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IEF1 EF EIE Figure 58. CSI/O Interrupt Request Generation CSI/O Operation The CSI/O is operated using status polling or interrupt driven algorithms. • Transmit–Polling a. Poll the TE bit in CNTR until Write the transmit data into ...
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Z8018x Family MPU User Manual 152 c. Poll the RE bit in CNTR until Read the receive data from TRDR. e. Repeat steps for each receive data byte. • Receive–Interrupts a. Poll the RE ...
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CSI/O and RESET During RESET each bit in the CNTR is initialized as defined in the CNTR register description. CSI/O transmit and receive operations in progress are aborted during RESET. However, the contents of TRDR are not changed. CKS TXS ...
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Z8018x Family MPU User Manual 154 CKS TXS 2.5f 7. Figure 60. UM005003-0703 LSB 2.5f 2.5f 2.5f 7.5f 7.5f Read or write of CSI/O Transmit/Receive Data Register Transmit Timing–External Clock MSB 7.5f ...
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CKS RXS LSB 11f 11f Sampling RE EF Figure 61. CSI/O Receive Timing–Internal Clock Family MPU User Manual MSB 11f 11f 17f Read or write of CSI/O Transmit/Receive Data Register UM005003-0703 Z8018x 155 ...
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Z8018x Family MPU User Manual 156 CKS RXS RE Figure 62. Programmable Reload Timer (PRT) The Z8X180 contains a two channel 16-bit Programmable Reload Timer. Each PRT channel contains a 16-bit down counter and a 16-bit reload register. The down ...
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The PRT input clock for both channels is equal to the system clock divided by 20. Internal Address/Data Bus Phi ¸ 20 Timer Data Timer Data Register 0L Register 0H : TMDR0L (8) Timer Control : TMDR0H (8) ...
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Z8018x Family MPU User Manual 158 return accurate data without requiring the timer to be stopped. The write procedure requires the PRT to be stopped. For reading (without stopping the timer), TMDR is read in the order of lower byte ...
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Timer Data Register 0L (TMDR0L: 0CH) Bit 7 6 Bit/Field R/W Reset Note Read W = Write X = Indeterminate ? = Not Applicable Timer Data Register 0H (TMDR0H: 0DH) Bit 7 6 Bit/Field R/W Reset Note: R ...
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Z8018x Family MPU User Manual 160 Timer Reload Register Channel 0L (RLDR0L: 0EH) Bit 7 Bit/Field R/W Reset Note Read W = Write X = Indeterminate ? = Not Applicable Timer Reload Register Channel 0H (RLDR0L: 0FH) Bit ...
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Timer Reload Register Channel 1L (RLDR1L: 16H) Bit 7 6 Bit/Field R/W Reset Note Read W = Write X = Indeterminate ? = Not Applicable Timer Reload Register Channel 1H (RLDR1H: 17H) Bit 7 6 Bit/Field R/W Reset ...
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Z8018x Family MPU User Manual 162 Bit Position Bit/Field R/W – – TIF1 0 R – – TIE1 0 R/W – – TOC1 0 R/W – – TDE1 0 R/W UM005003-0703 Value ...
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Table 23. Timer Output Control TOC1 TOC0 Figure 64 illustrates timer initialization, count down, and reload timing. Figure 65 depicts timer output (A18/TOUT) timing. Timer Data Register write (0004H) RESET Timer Data FFFFH 0004H Register Timer ...
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Z8018x Family MPU User Manual 164 Phi TOUT Figure 65. PRT Interrupts The PRT interrupt request circuit is illustrated in Figure 66. TIF1 TIE1 TIF0 TIE0 Figure 66. PRT and RESET During RESET, the bits in TCR are initialized as ...
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PRT Operation Notes • TMDR data is accurately read without stopping down counting by reading the lower (TMDRnL*) and higher (TMDRnH*) bytes in that order. Also, TMDR is read or written by stopping the down counting. Take care to ensure ...
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Z8018x Family MPU User Manual 166 These devices require connection with the Z8X180 synchronous E clock output. The speed (access time) required for the peripheral devices are determined by the Z8X180 clock rate. Table 24, and Figure 67 through Figure ...
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Op Code Memory Read/ Fetch Cycle Write Cycle Phi E M1 MREQ IORQ NOTE : MC = Machine Cycle Figure 67. E Clock Timing Diagram (During Read/Write Cycle and Interrupt Acknowledge Cycle Last state ...
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Z8018x Family MPU User Manual 168 SLP Instruction 2nd Op Code Fetch Cycle T1 Phi – INT, NMI E Figure 69. On-Chip Clock Generator The Z8X180 contains a crystal oscillator and system clock generator. A crystal can be ...
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Table 25. Z8X180 Operating Frequencies Clock Frequency Item Co Rs CL1, CL2 external clock input is used instead of a crystal, the waveform (twice the clock rate) must exhibit a 50% ± 10% duty ...
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Z8018x Family MPU User Manual 170 CL CL Note: Pin numbers are valid only for DIP configuration Figure 71. Figure 72. UM005003-0703 XTAL 2 EXTAL 3 Z8X180 Clock Generator Circuit Must be avoided A B Signal ...
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Crystal Z8X180 Top View Figure 73. Example of Board Design Circuit Board design should observe the following parameters. • Locate the crystal and load capacitors as close to the IC as physically ...
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Z8018x Family MPU User Manual 172 Miscellaneous Free Running Counter (I/O Address = If data is written into the free running counter, the interval of DRAM refresh cycle and baud rates for the ASCI and CSI/O are not guaranteed. In ...
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Software Architecture INSTRUCTION SET The Z80180 is object code-compatible with the Z80 CPU. Refer to the Z80 CPU Technical Manual or the Z80 Assembly Language Programming Manual for further details. Table 26. Instruction Set Summary New Instructions Operation SLP MLT ...
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Z8018x Family MPU User Manual 174 MLT- Multiply The MLT performs unsigned multiplication on two 8-bit numbers yielding a 16-bit result. MLT may specify BC, DE, HL registers. The 8-bit operands are loaded into each half of the ...
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TST (HL) - Test Memory The contents of memory pointed are ANDed with the accumulator (A) and the status flags are updated. The memory contents and accumulator are not changed (non-destructive AND). INO g, (m) - Input, ...
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Z8018x Family MPU User Manual 176 Figure 74 depicts CPU register configurations. Accumulator A B Register D Register H Register Accumulator A' B' Register D' Register H' Register Interrupt Vector Register I Index Register Index Register Stack Pointer Program Counter ...
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Flag Registers (F, F') The flag registers store status bits (described in the next section) resulting from executed instructions. General Purpose Registers (BC, BC', DE, DE', HL, HL') The General Purpose Registers are used for both address and data operation. ...
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Z8018x Family MPU User Manual 178 Stack Pointer (SP) The Stack Pointer (SP) contains the memory address based LIFO stack cleared to Program Counter (PC) The Program Counter (PC) contains the address of the instruction to be executed ...
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Bit Position Bit/Field R R/W 5 Not Used ? 4 H R/W 3 Not Used ? 2 P R/W Value Description 0 Zero set to 1 when instruction execution produces ...
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Z8018x Family MPU User Manual 180 Addressing Modes The Z80180 instruction set includes eight addressing modes. • Implied Register • Register Direct • Register Indirect • Indexed • Extended • Immediate • Relative • IO Implied Register (IMP) Certain Op ...
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Register field ' Register — 16-bit Register ...
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Z8018x Family MPU User Manual 182 Indexed (INDX) The memory operand address is calculated using the contents of an Index Register (IX or IY) and an 8-bit signed displacement specified in the instruction. Refer to Figure 77 displacement (d) Figure ...
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Immediate (IMMED) The memory operands are contained within one or two bytes of the instruction, as depicted in Figure 79. Op Code 8-bit m operand Figure 79. Immediate Addressing Relative (REL) Relative addressing mode is only used by the conditional ...
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Z8018x Family MPU User Manual 184 IO (I/O) IO addressing mode is used only by I/O instructions. This mode specifies I/O address (IORQ operand is output to A0–A7. The contents of accumulator is output to A8–A15. 2. ...
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DC Characteristics This section describes the DC characteristics of the Z8X180 family and absolute maximum rating for these products. ABSOLUTE MAXIMUM RATING Table 27. Absolute Maximum Rating Item Supply Voltage Input Voltage Operating Temperature Extended Temperature Storage Temperature Permanent IC ...