Z8018010PSG Zilog, Z8018010PSG Datasheet - Page 143

• Manufacturer Part Number: Z8018010PSG
• Description: IC 10MHZ Z180 CMOS ENH MPU 64DIP
• Manufacturer: Zilog

Specifications of Z8018010PSG

• Processor Type: Z180
• Features: 8-Bit, Enhanced Z80 Megacell
• Speed: 10MHz
• Voltage: 5V
• Mounting Type: Through Hole
• Package / Case: 64-DIP (0.750", 19.05mm)
• Processor Series: Z8018xx
• Core: Z80
• Data Bus Width: 8 bit
• Maximum Clock Frequency: 10 MHz
• Number Of Timers: 2
• Operating Supply Voltage: 0 V to 5 V
• Maximum Operating Temperature: + 70 C
• Mounting Style: Through Hole
• Minimum Operating Temperature: 0 C
• Core Size: 8bit
• Cpu Speed: 10MHz
• Digital Ic Case Style: DIP
• No. Of Pins: 64
• Supply Voltage Range: 4.5V To 5.5V
• Operating Temperature Range: 0°C To +70°C
• Svhc: No SVHC (18-Jun-2010)
• Base Number: 8018010
• Rohs Compliant: Yes
• Clock Frequency: 10MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 269-3889; Z8018010PSG

128
ASCI Control Register A 1 (CNTLA1: 01H)
UM005003-0703
Bit
Bit/Field
R/W
Reset
R = Read W = Write X = Indeterminate ? = Not Applicable
Bit
Position Bit/Field R/W
7
6
Z8018x
Family MPU User Manual
MPE
RE
MPE
R/W
7
0
R/W
R/W
R/W
RE
6
0
Value
R/W
TE
5
0
Description
Multi-Processor Mode Enable — The ASCI has a
multiprocessor communication mode which utilizes an
extra data bit for selective communication when a number
of processors share a common serial bus. Multiprocessor
data format is selected when the MP bit in CNTLB is set
to 1. If multiprocessor mode is not selected (MP bit in
CNTLB = 0), MPE has no effect. If multiprocessor mode
is selected, MPE enables or disables the wakeup feature as
follows. If MPE is set to 1, only received bytes in which
the MPB (multiprocessor bit) is 1 can affect the RDRF
and error flags. Effectively, other bytes (with MPB = 0)
are ignored by the ASCI. If MPE is reset to 0, all bytes,
regardless of the state of the MPB data bit, affect the
RDRF and error flags.
Receiver Enable — When RE is set to 1, the ASCI
receiver is enabled. When RE is reset to 0, the receiver is
disabled and any receive operation in progress is
interrupted. However, the RDRF and error flags are not
reset and the previous contents of RDRF and error flags
are held. RE is cleared to 0 in IOSTOP mode, and during
RESET.
CKA1D
R/W
4
0
MPBR/
R/W
EFR
3
X
MOD2
R/W
2
0
MOD1
R/W
1
0
MOD0
R/W
0
0